Under way
Implementation and Evaluation of Power Gating using an Advanced Technology Node
Type of work:
Master thesis
Assignment:
During this thesis, the student will focus on the design and modelling of the wrapping circuits and the creation of power gated islands with the help of UPF language. The implementation will mainly use the SystemVerilog for the extension of the RTL design and the Synopsys tools and design flow for the implementation and evaluation.
Skills:
- SystemVerilog (Verilog, RTL)
- UPF (unified power format) language
- Digital design
- Basic knowledge of Design Flows and Synthesis
Background:
Power Gating is a classical method to disable non-used circuits and to mitigate their leakage power consumption. Usually used for SRAMs or cores, the thesis should evaluate power gating in an advanced technology node (12nm) for an RTL-based hardware design.
Unified Power Format (UPF), a format to describe low power intent for design implementation, analysis and verification, is the latest standard developed by Accellera.
Supervisor:
Student:
Akash Biyani
Year:
2026