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Design and Implementation of UCIe Layers (for standard x16 package) using SystemVerilog Modelling

Type of work:

Master thesis

 
Assignment:

During this thesis, the student will focus on the design and modelling of the different UCIe layers, such as PHY layer, Die-to-Die adapter, and protocol layer. The implementation will mainly use the Raw or Streaming protocol for the layers to demonstrate the connectivity. 
The new UCIe specification in version 2.0 is the basis of this work, as well as other publications and presentations.

 
Skills:
  • SystemVerilog (Verilog, RTL)
  • UVM is an advantage
  • Digital design
  • Basic knowledge of analog components
 
Background:

UCIe is the extension of the communication standard PCIe towards chiplet-to-chiplet interconnect. 2D, 2.5D, or 3D integration can be used as infrastructure to connect different chiplet types. Originally invented by Intel and now widely spread to the community, the UCIe standard (version 2.0) offers various chip-to-chip communication possibilities.

Supervisor:

Dr. C. Weis, L. Birkenmeier

 
Student:

Student: Rustam Mammadli

 
Year:

2023