Design and Implementation of a low-power All-Digital Phase-Locked Loop

Type of work:

Master thesis

Assignment:

In this thesis, the student will design and implement an AD-PLL. The project will begin with the development of a Digitally Controlled Oscillator (DCO) using a fully digital design flow. Various design approaches will be explored, compared, and benchmarked against state-of-the-art analog and digital oscillators. The finalized DCO will then be integrated into a complete AD-PLL, with a focus on achieving a low-power implementation.

Skills:

• Digital FE tools (Genus/Design compiler)
• Digital BE tools (Innovus/IC Compiler 2)
• Verilog
• Analog/mixed-signal design (Virtuoso)
• Noise analysis and simulation (Spectre)
• Knowledge of advanced technology nodes is a plus
• System-level modelling (Verilog-A/Python/MATLAB) is a plus

Background:

All-Digital Phase-Locked Loops (AD-PLLs) have gained widespread adoption over the past few decades due to their compact size, lower power consumption, and greater versatility compared to analog counterparts. A key advantage of AD-PLLs is their independence from specific technologies. However, the effective full-digital implementation of the oscillator, the core component of any PLL, remains a challenge, and significant research is still required to achieve a competitive solution.

Supervisor:

M. Mestice

Student:

Furkan Aktas

Year:

2025