Comparison of Low-Bitwidth Data Formats for DSP and AI Applications

Type of work:

Master thesis

Assignment:

 In this thesis, the student will investigate and implement digital circuits utilizing state-of-the-art low-bitwidth data formats (e.g., FP8, FP6, FP4, INT8) for core arithmetic operations and composite functions relevant to Digital Signal Processing (DSP) and Artificial Intelligence (AI) workloads. The work includes developing and benchmarking custom adders and multipliers, as well as integrating these into higher-level operations (such as dot product, FIR filters, and FFTs), and ultimately applying them to practical use cases like Convolutional Neural Networks (CNNs) and Orthogonal Frequency Division Multiplexing (OFDM) signal processing. All designs will be evaluated under power, performance, and area (PPA) constraints, aiming to provide guidelines for optimized hardware design in embedded environments. The student will also deliver a reusable framework to facilitate future research in low-bitwidth arithmetic architectures.

Skills:

• Signal Processing
• RTL (SystemVerilog, Verilog)
• Digital design

Background:

As Moore’s Law slows, the need for efficient hardware in computation-intensive applications is driving interest in custom accelerators and alternative number formats. Low-bitwidth data representations promise significant reductions in power, area, and latency for embedded DSP and AI workloads, but introduce trade-offs in terms of numerical accuracy and architectural complexity. While research in this area has produced promising formats and arithmetic techniques (including LNS-based operations), there remains a lack of comparative data and systematic frameworks for evaluating their performance across relevant applications. This thesis addresses these gaps, providing actionable insights for future hardware design targeting embedded signal processing and machine learning.

Supervisor:

L. Krupp

Student:

Gustavo Magalhães Gomes De Souza

Year:

2025