Bridging the gap between AXI4 to UCIe Physical Channel using an Advanced Technology Node

Type of work:

Master thesis

Description:
 

This master’s thesis aims to develop a full demonstrator for an attachable UCIe Physical Channel (off-chip) using AXI4 (on-chip) as classical SoC interface for data and code transfers. The work focuses on designing a dedicated hardware architecture that uses standard UCIe interfaces and a scalable AXI4 bridge to combine these interconnect (on-chip bus and off-chip) interfaces. The objective is to achieve equivalent bandwidths for both sides (interfaces) at lowest possible latencies for read and write. Finally, an evaluation of PPA using Synthesis and Place&Route will be performed.

Supervisor:

C. Weis,  M.Mestice

Student:

Armin Amiri Sani

Year:

2025