Design and Implementation of Write and Read Grouping in a LPDDR5 Memory Controller

Type of work:

Master thesis

Assignment:
 

In this thesis, the student will design and implement an update to the existing LPDDR5 memory controller so that write/read commands are grouped together to improve the overall performance of the memory controller. The work includes developing a logic unit that can sort different request types, feed the commands into a processing pipeline, and simultaneously keep track of dependencies in the requests. Furthermore, a redesign of the bank manager will be performed to accommodate the out-of-order operation of the implemented scheduler. To compare the updated memory controller with its predecessor, a synthesis will be performed, and multiple aspects such as performance, power, and area will be inspected. The student will develop the modifications in such a way that the new ordering scheme can be applied to other memory controller types (DDR4 or LPDDR4X).

 

Skills:  
 

• DRAM
• Memory Controller
• RTL (SystemVerilog, Verilog)
• Digital design
   

Background: 

In response to the growing demand for more powerful and energy-efficient mobile devices, the requirements for their components have increased significantly. Modern software demands large amounts of data and low access times, which present substantial challenges for memory systems. In the communication between the CPU and storage, the bus between the DRAM and CPU becomes a bottleneck. This bottleneck worsens if the bus timing is not utilized optimally. Although our memory controller already applies several timing-optimization techniques to improve bus utilization, one major optimization potential was previously left unexplored to preserve a simpler controller design. However, due to increasing performance demands, a first step toward reordering is now taken by grouping write and read commands together. Such reordering can reduce idle bus time between the memory controller and DRAM since switching from writing to reading-or vice versa-requires additional idle cycles. This thesis addresses these inefficiencies in bus utilization, demonstrating the potential performance improvements as well as the increased complexity introduced by reordering.

Supervisor:

C. Weis, S. Dauber

Student:

Ifra Naseer

Year:

2025