In multicore platforms, handling processing units only does not suffice, as the impact of other resources, such as buses, caches and -hierarchies, memory accesses etc. is non negligible, these have to be taken into account explicitly. The durations of memory accesses vary by orders of magnitude depending on on-chip or off-chip locations, for example. To complicate matters even more, interdependencies exist e.g., due to contention on buses or caches: scheduling of tasks determines when memory accesses take place, i.e., when the task may require a transfer over the bus, which will effect the execution time of the task, which in turn will effect the schedule, a circular dependency. This impacts methods for safety or timeliness profoundly.
We have been developing methods for
- safe execution on COTS multi-core platforms based on coordinated platform resource provisioning and regulation, validated with an avionics setting in collaboration with Airbus
- safe monitoring of task progress in general purpose multi-core platform and operating system for early detection in an autonomous driving setting with Huawei
- methods for core-failure migitation in safety critical applications in collboration with Thales and ONERA.