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• Architecture-Driven Voltage Scaling for High-Throughput Turbo-Decoders
• A Scalable System Architecture for High-Throughput Turbo-Decoders
• Advanced Architectures for High-Throughput Turbo-Decoders
• Architecture-Driven Voltage Scaling for High-Throughput Turbo-Decoders
• Low Complexity Stopping Criteria for UMTS Turbo-Decoders
• Communication Centric Architectures for Turbo-Decoding on Embedded Multiprocessors
• Concurrent Interleaving Architectures for High-Throughput Channel Coding
• Efficient MAP-Algorithm Implementation on Programmable Architectures
• A Scalable System Architecture for High-Throughput Turbo-Decoders
• Optimized Concurrent Interleaver Architecture for High-Speed Turbo-Decoding
• Evaluation of Algorithm Optimizations for Low-power Turbo-Decoder Implementations
• Algorithmische Transformationen zur Reduktion des Leistungsverbrauchs in fortgeschrittenen Kanalcodierungsverfahren
• Algorithm Manipulation for Low-Power Communication Circuit Implementation
• Voltage Scheduling Algorithms for UMTS Turbo-Code Decoding on Variable Supply Voltage Processors
• Low Power Implementation of a Turbo-Decoder on Programmable Architectures