Sascha Maurice Dauber
Design and Implementation of a LPDDR5 DRAM Controller for ASIC Integration (Diplomarbeit)
Supervisor:  C. Weis

Sayed Mohammad Tariful Azam
ASIC-based hardware acceleration of Algebraic Machine Learning  (Master Thesis)
Supervisor:  M. Hassani Sadi, C. Weis

Hiandra Tomasi
Custom Processor Instructions for SHA3 on RISC-V Architecture: A Design Space Exploration for FPGA and ASIC Implementation  (Master Thesis)
Supervisor: M.Schöffel

José Cabrera
Implementation of a Doppler Channel Model for Low Earth Orbit Satellites (Master Thesis)
Supervisor: J. Ney

Ghada Chams Zahrouni
Design and Implementation of a Face Recognition System on a Hybrid Xilinx Zynq SoC Demonstrator (Master Thesis)
Supervisor: C. De Schryver

Amine Riahi
Investigating Emerging Trends in Logic Circuit simulation with emphasis on interconnect modeling (Master Thesis)
Supervisor: J. Lappas

Taha Chiheb
Power characterization of external SRAMs with serial interface (Bachlor Thesis)
Supervisor: J. Feldmann

Sascha Dauber
Detailed Behavioral Modelling of an Initialization Unit for a DRAM PHY (Student Thesis)
Supervisor: C. Weis

Lukas Boos
Development of a System for Ambient Light Control in Modern Vehicles (Master Thesis)
Supervisor: C. De Schryver

Daniel Vedaa
System-Level Modelling of the ONFI Standard (Master Thesis)
Supervisor: Matthias Jung, Lukas Steiner

Gizem Amati
Development and Implementation of an Autonomous Temperature Control System for Smart Building Environments (Master Thesis)
Supervisor: C. De Schryver

Ahmad Abdulla
Embedded Air write: Implementation of Movement Reconstruction (trajectory reconstruction) Algorithm on CPU, GPU and FPGA for real time performance (Master Thesis)
Supervisor: M.M.Ghaffar

Derek Christ
Development of a System-Level Simulation Frontend for DRAMSys (Bachlor Thesis)
Supervisor: Matthias Jung, Lukas Steiner

Mohamed Moursi
Exploration of Memory Partitioning for Streaming Architectures for Encoder-Decoder Based DNNs (Master Thesis)
Supervisor: Mohsin Gaffer, Jonas Ney, Vladimir Rybalkin

Ali Shamya
HW/SW Codesign for RISC-V based LPDDR4X-PHY Management Controller (Master Thesis)
Supervisor: Johannes Feldmann, Jan Lappas

Jakob Sherif
Design, Implementation, and Evaluation of a Prediction System Based on Non-Invasive Sensors (Bachelor Thesis)
Supervisor: Christian De Schryver

Yazan Kazhalawi
Investigation on Layered Decoding Schedules for LDPC Codes (Bachelor Thesis)
Supervisor: Matthias Herrmann, Oliver Griebel

Maria Feting
Acceleration of a High Secure Hashing Algorithm using Near Memory Computing on a Custom RISC-V Platform (Master Thesis)
Supervisor: Johannes Feldmann, Max Schöffel

Bryan Olmos
Formal Verification of DRAM Controllers Using Timed Petri Nets (Master Thesis)
Supervisor: Lukas Steiner, Chirag Sudarshan

Mohamed Amine Riahi
A Pass-Transistor-Logic Compatible STA Engine for Path-based Delay Optimization (Bachelor Thesis)
Supervisor: André Chinazzo, Jan Lappas

Iris Walter
Performance-Accuracy Trade-off Analysis, Efficient Design and Implementation of a Deep Neural Network for Face Recognition on FPGAs (Master Thesis)
Supervisor: Vladimir Rybalkin

Elias Batbouta
Vergleich des Standes der Technik von auf Speichertechnologien basierenden Physical-Unclonable-Functions (Project)
Supervisor: Christian Weis

Lucas Weber
Evaluation of Quantum-Safe Digital Signature Algorithms in the Context of TLS-based Low-Power IoT (Master Thesis)
Supervisor: Maximilian Schöffel, Frederik Lauer

Melanie Neudecker
Entwicklung eines Klassifikationsmodells zur Bestimmung von Qualitätsparametern von Maissilage anhand von Deep Learning auf Grundlage von Hyperspektraldaten (Master Thesis)
Supervisor: Christian Weis

Luiza Souza Correa
Power Estimation of Modern DRAM Memories (Master Thesis)
Supervisor: Christian Weis

Rosy Elizabeth Sebastian
Systolic Array Based Quantized Neural Network Accelerator with Custom Memory Hierarchy to Minimize Off-Chip Transfers (Master Thesis)
Supervisor: Muhammad Mohsin Ghaffar

Patrick Eckes
Design and Evaluation of a Low-cost Infrared Camera-based Positioning System (Master Thesis)
Supervisor: Frederik Lauer

Stephan Stürz
Analysis and Exploration of hardware-aware Compression Techniques for Deep Neural Networks (Bachelor Thesis)
Supervisor: Jonas Ney

Lukas Boos
Konzeption, Aufbau und Validierung einer intelligenten Gartenbewässerungssteuerung (Bachelor Thesis)
Supervisor: Christian De Schryver

Alexander Ehre
Konzeption und Entwicklung eines RFID basierten Scannersystems für die produzierende Industrie (Studienarbeit)
Supervisor: Christian De Schryver

Julia Rützel
Konzeption und Entwicklung eines SmartBuilding-Simulators auf Basis von KNX (Bachelor Thesis)
Supervisor: Christian De Schryver

Mouayad Horani
Flexible High Throughput Polar Decoders (Master Thesis)
Supervisor: Claus Kestel

Heba Ganem
Efficient FEFET-based Crossbar and Mixed-signal Blocks Design for an In-memory DNN Hardware Accelerator (Master Thesis)
Supervisor: Taha Soliman, Chirag Sudarshan

Ahmed EL-Yamany
Exploration of Deep Neural Network Topologies and Efficient Hardware Architecture for Historical Document Baseline Detection (Master Thesis)
Supervisor: Vladimir Rybalkin

Ebin Zacharias
Deep Learning-based Scene Text Recognition in Mobile Outdoor Application (Master Thesis)
Supervisor: Vladimir Rybalkin, Menbere Tekleyohannes

Jonas Ney
A Hardware Architecture of a Deep Convolutional Encoder-Decoder Network for Page Segmentation of Historical Handwritten Documents (Master Thesis)
Supervisor: Vladimir Rybalkin, Muhammad Mohsin Ghaffar

Stefan Pajonk
Exploration and Benchmarking of Memory Architecture Using Virtual Prototyping (Master Thesis)
Supervisor: Éder Ferreira Zulian

Yannick Robin
Generic On-Chip Memory Generator for ASIC Design Exploration (Master Thesis)
Supervisor: Jan Lappas

Felipe Salerno Prado
A Domain-Specific Language for Describing DRAM Behavior (Master Thesis)
Supervisor: Christian Weis, Matthias Jung (IESE)

Khalil Esper
Implementation and Evaluation of Industry 4.0 Service-oriented Production Using Revolution Pi (Master Thesis)
Supervisor: Christian Weis, Matthias Jung (IESE)

Manoj Hanumaiah
Evaluation and Implementation of an Indoor Localization System for Fraunhofer IESE Concept Cars (Master Thesis)
Supervisor: Matthias Jung, C. Peper (IESE), Christian Weis

Oliver Broschart
Automated Design and Implementation of a DDR4 Receiver (Master Thesis)
Supervisor: Jan Lappas, Christian Weis

Lukas Steiner
Simulation of Emerging Memory Standards with DRAMSys (Master Thesis)
Supervisor: Matthias Jung, Christian Weis

Patrik Eckes
Sensor Fusion Approaches for the Detection of Door and Window Events in Buildings (Bachelor Thesis)
Supervisor: Frederik Lauer, Carl Rheinländer

Kirill Bykov
A SystemC/TLM Framework for Characterising and Validating the RTL Implementation of a Memory Controller (Master Thesis)
Supervisor: Chirag Sudershan, Matthias Jung

Daniel Rühm
Development of an Input Device with Steam VR Tracking (Master Thesis)
Supervisor: Christian Weis, Ricardo A. Tauro (ITK)

David Schall
Investigation and Evaluation of hardware-based Memory Encryption and Integrity (Master Thesis)
Supervisor: Christian Weis, Andreas Sandberg (ARM)

Daniel Gretzke
Design and Implementation of a Blockchain-Based Smart Outlet Concept (Bachelor Thesis)
Supervisor: Carl Rheinländer, Frederik Lauer

Josua Mayer
Development of a transparent Gateway for Internet of Things Devices using IPv6 over Bluetooth Low Energy (Bachelor Thesis)
Supervisor: Carl Rheinländer, Frederik Lauer

Jens Ullmert
Design of an FMC compatible eMMC Adapter Board for Hybrid Memory Emulations (Bachelor Thesis)
Supervisor: Carl Rheinländer

Maxmilian Moritz Schöffel
Design and Implementation of a Hybrid Memory Controller (Master Thesis)
Supervisor: Deepak M. Mathew

Claudien Nyituriki
A High-Level Implementation of a Hybrid Memory Controller for DRAM and NVM (Diplomarbeit)
Supervisor: Deepak M. Mathew

Surabhi Jain
Parallelism Selection For Performance Improvement Under Area Constraints In Systems With FPGA Accelerators (Master Thesis)
Supervisor: Christian Weis

Ivi Prifti
RTL Design, Verification, ASIC Implementation of an LPDDR4 Memory Controller and Research on Feasible Schedulers (Master Thesis)
Supervisor: Chirag Sudarshan

Anjie Qiu
Window Skipping for Unrolled Turbo Decoders (Master Thesis)
Supervisor: Stefan Weithoffer

Rodrigo Cortes Porto
Integration of SystemC-AMS Simulation Platform into TTool (Master Thesis)
Supervisor: Christian Weis

Mhd. Rashed Al Koutayni
Hardware Implementation of CNN-Based Hand Pose Estimation on FPGA (Master Thesis)
Supervisor: Vladimir Rybalkin

Vitor Ribero Roriz
Development of a High-level TCP/IP Driver for a Message-passing Real-time Operating System (Master Thesis)
Supervisor: Christian Weis

Anes Benmerzoug
Hardware Aware Training and Architecture Exploration For a Multi-Dimensional LSTM Neural Network (Master Thesis)
Supervisor: Vladimir Rybalkin

Manikantan Ravichandran
RISC-V based Reconfigurable Deep Learning Accelerator Framework Implemented on FPGAs (Master Thesis)
Supervisor: Christian Weis

Johannes Feldmann
An Application Specific Memory Controller for Video Stream Processing (Master Thesis)
Supervisor: Christian Weis

Christopher Schmidt
Ein Generatortool für abgerollte vollparallele LDPC Code Decoder (Studienarbeit)
Supervisor: Matthias Herrmann

Yannick Robin
Comparative Study on Different Types of DRAM Sense-Amplifier Implementations for In-Memory-Processing (Bachelor Thesis)
Supervisor: Jan Lappas

Niklas Thiedecke
CORDIC-Hardwareimplementierung mit erweitertem Funktionsumfang und erweitertem Konvergenzbereich (Bachelor Thesis)
Supervisor: Christian Weis

Lukas Krupp
Zeitliche Synchronisation von Basisstationen in drahtlosen Netzwerken für einen echtzeitfähigen Handover-Mechanismus (Bachelor Thesis)
Supervisor: Carl Rheinländer

Doris Gulai
Modeling of LPDDR4-DRAM in DRAMSys (Bachelor Thesis)
Supervisor: Christian Weis

Lukas Steiner
Hardware Implementation & Evaluation of Morphological Reconstruction Filter (Bachelor Thesis)
Supervisor: Menbere Tekleyohannes

Jonas Ney
Exploration of a New All Programmable Heterogeneous MPSoC Computing Platform Xilinx Zynq Ultra Scale+ with Application to Machine Learning (Bachelor Thesis)
Supervisor: Vladimir Rybalkin, Menbere Tekleyohannes

André Lucas Chinazzo
ReRAMSpec: High-Level Modelling of High Density Resistive RAM Cross-Point Arrays (Master Thesis)
Supervisor: Deepak Mathew, Christian Weis

Frederik Lauer
High Secure Ultra Low Power IoT Infrastructure Exploration (Master Thesis)
Supervisor: Carl Rheinländer, Claus Kestel

Chetan Dobariya
Design and Implementation of an eDRAM Array using a 2T Gain Cell in UMC’s 65 nm Technology (Master Thesis)
Supervisor: Christian Weis

Amir Massah Bavani
An Efficient Reconfigurable Hardware Accelerator for Deep Convolutional Neural Network using 3D Systolic Arrays (Master Thesis)
Supervisor: Vladimir Rybalkin, Muhammad Mohsin Ghaffar

Maycon Douglas Da Silva Carvalho
A heterogeneous embedded computing system for parallel processing of frames extracted from real-time video streams (Master Thesis)
Supervisor: Carl Rheinländer, Christian Weis

Martin Zeyen
Untersuchung des Noisy Gradient Descent Bit-Flipping Algorithmus zum Decodieren von LDPC Codes (Diplomarbeit)
Supervisor: Kira Kraft, Stefan Weithoffer

Nkrumah Offonry
An Empirical Exploration of Different ECCs for Next-Generation DRAMs and Memories (Master Thesis)
Supervisor: Christian Weis

Anjie Qiu
Implementation and Evaluation of the Belief-Propagation Algorithm for LTE-Turbo-Codes (Bachelor Thesis)
Supervisor: Stefan Weithoffer