Here you will find the lectures offered by our working group in the winter semester.

A list of vacant student works can be found here.

Contents

Content of this lab are the modeling and extension of a typical RISC processor architecture (RiscV). Students must realize the concepts of modern processor architectures (e.g. forwarding or memory caches) in hardware (synthesizable VHDL / Verilog models) and analyze the runtime performance of processors. Additionally the concept of Application Specific Instruction Processor (ASIP) is trained. Furthermore students acquire skills in hardware validation and use of typical EDA tools (e.g. synthesis) in large projects.

Contents

• Design of digital CMOS circuits
• The MOS transistor
• Leakage mechanisms
  
• Advanced transistor technologies
  
• Introduction to the CMOS process
• Design methodologies
• Implementation styles and technologies
• Circuit techniques
• Sequential circuits

Contents

• Various terms and definitions of probability
• Stochastic independence, joint experiments
• Random Variables (ZV) and moments
• Special distributions of continuous and discrete random variables, multi-dimensional random variables, covariance matrix
• Application examples: reliability theory and safety
• Mathematical statistics, parameter estimation, confidence estimators

Contents

Base knowledge is provided to specify the base components of digital logic in VHDL. Furthermore the designed circuits must be verified by simulation and will be synthesized to FPGA devices.

Basics of the hardware description language VHDL and explanation of the tasks will be given Tuesdays 11:45-13:15 in 13-222. Further teaching material is provided in the OLAT system.

Kick-Off meeting will be on Tuesday 29. Oktober 2024, 11:45-13:15 in 13-222.

Contents

Lecture series with following lecturers:

• Prof. Dr.-Ing. Hans D. Schotten
• Prof. Dr.-Ing. Steven Liu
• Jun. Prof. Dr.-Ing. Daniel Görges
• Prof. Dr.-Ing. Norbert Wehn

Content from our side:

• Introduction to processors and computing systems
• Real world processor example: Aurix
• Introduction to Safety
• Virtual prototyping with SystemC TLM

Contents

In this 4-day course the basic knowledge in using hardware description language VHDL with EDA tools is given. Implementation of digital circuits on base of FPGAs (and standard cells) will be teached in english language. This course is provided only for master students without any knowledge of hardware description languages (VHDL or Verilog).

Registration: Email

• Design space and simulation model of VHDL
• Realization of behavioral description with hardware description language VHDL
• Using of synthetizable subset of VHDL and introduction to synthesis
• Realization of a decoder for the radio time signal DCF-77 for radio clocks
• Design flow and constraints for realization of application specific integrated circuits, especially with Xilinx FPGA technologies

Contents

Talks and discussions related to microelectronics

• #SWS: 2 h
• #ECTS Credits: 3
• Languages: German / English
• Registration mandatory: yes

Contents

The lecture Synthesis and Optimization of Microelectronic Systems addresses students in electrical engineering, computer engineering and computer science who are interested in design automation of hardware dominated embedded systems. It introduces the whole implementation chain from systems specification down to implementation on register transfer level.

Covered topics

• Motivation
• System Modelling and Specification
• Hardware/Software Partitioning
• High level synthesis techniques: Scheduling, Allocation, Binding
• Register-Transfer Synthesis

Contents

• Introduction to virtual prototyping and virtual product development methodology for embedded systems
• System models and specification
• Hardware/Software co-development with virtual prototyping
• Modelling with cycle accurate SystemC
• Modelling on higher level of abstraction with Transaction Level Modeling (TLM)

Contents

The recent advances in deep learning, enabling the use of deep neural networks in various industrial applications, have been fueled by the availability of tremendous computing power. Their resource requirements are a critical limiting factor for the applicability of deep learning methods, especially in embedded systems where the resources are inherently scarce. Therefore, this course covers techniques for the design of resource-efficient hardware-software systems targeting machine learning workloads. The focus lies on the cross-layer view, jointly considering the application, algorithm, hardware architecture, and computing platform. Students will explore core concepts like neural network models, resource requirements of their training and inference, and hardware platforms like GPUs, FPGAs, or microcontrollers for AI applications. The course delves into optimization techniques, including quantization, pruning, and hardware-aware neural architecture search (NAS). Practical hands-on experience will be provided in hardware accelerator design and mapping AI algorithms to efficient hardware architectures.