PD Dr.-Ing. habil. Frank Kienle
Address
Roche Diagnostics GmbH
Sandhofer Strasse 116
68305 Mannheim
Contact
Email: lecture(at)kienlefrank.de
Frank Kienle worked for Blue Yonder from 01/2013 to 09/2017, first as a senior data scientist, later as director data science consulting. He is convinced that Industry 4.0 marks the beginning of a new era in which a strong combination of modern software methods and traditional engineering education becomes mandatory. His main focus topics are with machine learning applications and artificial intelligence systems, with focus on delivering value for the customer. Since 10/2017 he is working at Camelot ITLabs and is head of the competence center artificial intelligence and data science.
Frank Kienle, doctor in electrical engineering, has more than 10 years experience in data processing and modern algorithms. From 2006 to 2012 he was an academic advisor at the Technical University Kaiserslautern (TUK). During this time he supervised numerous industrial projects and lectured at the microelectronic systems design research group and the Karlsruhe Institute of Technology (KIT). Since 2014 he gives the lecture 'Introduction to Data Science' at TUK.
Courses
Research Areas since 2013
- predictive analytics
- data science
- big data applications
Research Areas until 2013
- LDPC and TC decoder architectures
- Binary/Duo-Binary Turbo-Codes
- Multi-dimensional Turbo-Codes
- Multi-edge type LDPC Codes
- LDPC Codes for hybrid ARQ
- Low-Density MIMO Codes
- Iterative MIMO Demodulation
Publications
- Integer Programming as a Tool for Analysis of Channel Codes
- Architectural challenges for high-throughput iterative MIMO systems
- A 2.15GBit/s Turbo Code Decoder for LTE Advanced Base Station Applications
- ML vs. BP Decoding of Binary and Non-Binary LDPC Codes
- A System View on Iterative MIMO Detection: Dynamic Sphere Detection versus Fixed Effort List Detection
- ASIC Design of a Gbit/s LDPC Decoder for Iterative MIMO Systems
- An Energy Efficient FPGA Accelerator for Monte Carlo Option Pricing with the Heston Model
- On Complexity, Energy- and Implementation Efficiency of Channel Decoders
- Architecture and Hardware Requirements for Turbo and LDPC decoders
- A Lagrangian relaxation based decoding algorithm for LTE Turbo codes
- Calculating the Minimum Distance of Linear Block Codes via Integer Programming
- A Separation Algorithm for Improved LP-Decoding of Linear Block Codes
- Sphere-Decoder-First Channel Code Design
- Numerical Comparison of IP Formulations as ML decoders
- Space-Time Bit Trellis Codes
- Valid Inequalities for Binary Linear Codes
- On Low-Density MIMO Codes
- A Novel LDPC Decoder for DVB-S2 IP
- A Separation Algorithm for Improved LP-Decoding of Linear Block Codes
- Low-Density MIMO Codes
- A Technical View on the URANUS Validation Platform
- Macro Interleaver Design for Bit Interleaved Coded Modulation with Low-Density Parity-Check Codes
- A Survey on LDPC Codes and Decoders for OFDM-based UWB Systems
- Low Complexity LDPC Code Decoders for Next Generation Standards
- Turbo-Codes vs. LDPC Codes (invited Talk)
- Design of Irregular LDPC Codes for Flexible Encoder and Decoder Hardware Realizations
- A Synthesizable IP Core for WIMAX 802.16E LDPC Code Decoding
- Enhanced Channel Coding for OFDM-based UWB Systems
- Fast Convergence Algorithm for LDPC Codes
- Disclosing the LDPC Code Decoder Design Space
- Low Complexity Stopping Criterion for LDPC Code Decoders
- A synthesizable IP Core for DVB-S2 LDPC Code Decoding
- Efficient Hardware Realization of IRA Code Decoders
- Joint Graph-Decoder Design of IRA-Codes on Scalable Architectures
- Design Methodology for IRA Codes
- Advanced Architectures for High-Throughput Turbo-Decoders
- A Survey on LDPC- and Turbo-Decoder Implementations
- Implementation Issues of Scalable LDPC-Decoders
- Low Complexity Stopping Criteria for UMTS Turbo-Decoders
- VLSI-Implementation Issues of Turbo Trellis-Coded Modulation
- Efficient MAP-Algorithm Implementation on Programmable Architectures