Filling The Large White Plain


The European Commission wants to enable the EU to achieve its goal of doubling its current market share to 20% by 2030. This concerns various aspects of chip development, from the ability to implement functions to the availability of developers.
This talk will focus on ways to increase productivity in chip design, but also on facilitating access to semiconductor design. The example of IP development at MINRES Technologies GmbH will be used to illustrate how this can be achieved through abstraction and a paradigm shift.

Eyck Jentzsch

MINRES Technologies GmbH

Eyck Jentzsch holds a Dipl-Ing. from the Technical University Ilmenau and has more than 25 years experience in microelectronics and semiconductor design. He is working at MINRES as General Manager and focuses on virtual platform modelling, development, and application in software development as well as hardware design & verifcation. Prior to that he worked at Cadence Design Systems Inc. and Siemens in various full- and semi-custom as well as system level design and verification positions.  


Eyck Jentzsch hat sein Studium der Elektrotechnik an der Technischen Universität Ilmenau als Diplom-Ingenieur abgeschlossen. Er verfügt über mehr als 25 Jahre Erfahrung in Mikroelektronik und Halbleiterentwurf. Er arbeitet bei MINRES als Geschäftsführer und konzentriert sich auf die Modellierung, Entwicklung und Anwendung virtueller Plattformen sowie deren Verwendung für die Hardwareverifikation. Zuvor war er bei Cadence Design Systems Inc. und Siemens in verschiedenen Positionen im Full- und Semi-Custom- sowie System-Level-Design und in der Verifikation tätig.