Room: 12/543

Tel: (+49) (631) 205 2609

E-Mail: fadiheh(at)eit.uni-kl.de

GitHub: https://github.com/mofadiheh

Courses: 

• Verification of Digital Systems Lab

Research Interests:

Mohammad R. Fadiheh mainly works in the field Formal HW Security verification techniques and secure HW design. The previous works and publications mainly cover:

• Formal verification techniques targeting transient execution attacks
• Design and verification of secure speculation in out-of-order execution processors
• Transient execution side channel attacks
• Processor verification

Publications:

• L. Deutschmann, J. Müller, M. R. Fadiheh, D. Stoffel, and W. Kunz, “Towards a Formally Verified Hardware Root-of-Trust for Data-Oblivious Computing”, 59th IEEE/ACM Design Automation Conference (DAC'22), San Francisco, July 2022. (Best Paper Award )
   
• M. R. Fadiheh, Alex Wezel, Johannes Müller, Joerg Bormann, Sayak Ray, Jason M Fung, Subhasish Mitra, Dominik Stoffel, and Wolfgang Kunz, "An Exhaustive Approach to Detecting Transient Execution Side Channels in RTL Designs of Processors," in IEEE Transactions on Computers, doi: 10.1109/TC.2022.3152666.

• J. Müller, M.R. Fadiheh, A. Duque-Anton, T. Eisenbarth, D. Stoffel, W. Kunz: "A Formal Approach to Confidentiality Verification in SoCs at the Register Transfer Level", To be published in 58th Annual Design Automation Conference, (DAC'21), 2021
   
• M.R. Fadiheh, J. Müller, R. Brinkmann, S. Mitra, D. Stoffel, W. Kunz: A formal approach for detecting vulnerabilities to transient execution attacks in out-of-order processors. 57th Annual Design Automation Conference, (DAC'20), 2020
   
• M.R. Fadiheh, J. Müller, A. Duque-Anton, S. Mitra, J. Fung, D. Stoffel, W. Kunz: A Systematic Approach to Detecting Microarchitectural Security Vulnerabilities by RTL Hardware Verification, Intel Side-Channel Academic Program (SCAP) Workshop 2020, (recording: https://wolke12.eit.uni-kl.de/index.php/s/2XAfUaaT8VLnOZy)
   
• M.R. Fadiheh, J. Müller, A. Duque-Anton, S. Mitra, D. Stoffel, W. Kunz: A Formal Approach for Detecting Vulnerabilities to Transient Execution Attacks in Out-of-order Processors, Intel Side-Channel Academic Program Workshop (SCAP) 2020, (recording: https://wolke12.eit.uni-kl.de/index.php/s/b7fWl5WA4iKTGY3)
   
• K. Devarajegowda, M.R. Fadiheh:"C-S2QED: Gap-Free Formal Verification of Processor Cores",Design and Verification Conference Europe (DVCON EU), Virtual Conference, October. 2020.
   
• K. Devarajegowda, M.R. Fadiheh, E. Singh, C. Barrett, S. Mitra, W. Ecker, D. Stoffel, W. Kunz: "Gap-free Processor Verification by S²QED and Property Generation", Design, Automation Test in Europe Conference Exhibition (DATE), Grenoble, March 2020
   
• M.R. Fadiheh, D. Stoffel, S. Mitra, C. Barrett, W. Kunz: ”Processor hardware security vulnerabilities and their detection by unique program execution checking”. Design, Automation Test in Europe Conference Exhibition (DATE), Florence, March 2019.
   
• M.R. Fadiheh, D. Stoffel, S. Mitra, C. Barrett, W. Kunz: ”Processor hardware security vulnerabilities and their detection by unique program execution checking (extended version)”. arXiv:1812.04975, link: https://arxiv.org/pdf/1812.04975.pdf
   
• E. Singh, K. Devarajegowda, S. Simon, R. Schnieder, K. Ganesan, M.R. Fadiheh, D. Stoffel, W. Kunz, C. Barrett, W. Ecker and S. Mitra: "Symbolic QED pre-silicon verification for automotive microcontroller cores: Industrial case study." Design, Automation Test in Europe Conference Exhibition (DATE), Florence, March 2019.
   
• M.R. Fadiheh, S.S. Nuthakki, S. Mitra, C. Barrett, D. Stoffel, W. Kunz: ”Symbolic quick error detection using symbolic initial state for pre-silicon verification.” In Design, Automation Test in Europe Conference Exhibition (DATE), 2018 (pp. 55-60).