I'm researching in the field of  system level design. My goal is to bridge the gap between system level(Transaction level) description and RT-level descriptions. This is archived by using properties that are extracted from system level design and have to  be verified for the designed hardware.

The main focus right now is to generate a complete set of properties from a system level description and use those properties to do a property-driven hardware development, similar to test-first software development. 

Working with:

• SystemC
• SVA
• VHDL
• Onespin