Contact : +49 631 205 2685

Email : udupi(at)eit.uni-kl.de

Office : 12-545

"I am pursuing a Ph.D at the Electronics Design Automation group headed by Prof. Wolfgang Kunz, at the University of Kaiserslautern. My research is in the area of applying the results of formal hardware verification to optimize non-functional aspects of the design like power and safety. I have an M.S in EE from Uni KL and a B.E in EE from RVCE, Bangalore."

List of Publications:

S. Udupi, J. Urdahl, D. Stoffel and W. Kunz, "Dynamic Power Optimization Based on Formal Property Checking of Operations," 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID), Hyderabad, 2017

 

J. Urdahl, S. Udupi, T. Ludwig, D. Stoffel, W. Kunz: Properties First? A New Design Methodology for Hardware, and its Perspectives in Safety Analysis, IEEE/ACM International Conference on Computer Aided Design (ICCAD), Austin, USA, 2016

 

J. Urdahl, S. Udupi, D. Stoffel, W. Kunz: "Formal System-on-Chip Verification: An Operation-Based Methodology and its Perspectives in Low Power Design", Proc. 23th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS'13), September 20