Announcement: EIT Kolloquium with Mike O‘Connor

The lecture takes place on Friday, 3 February 2017 at 11:00 am, in Building 12, Room 270, at the University of Kaiserslautern.

Abstract:

High-bandwidth, energy-efficient DRAM architectures arerequired to support the computation demands of GPUs (andother throughput architectures). This talk describes severalaspects of GPU memory systems, with a focus on therequirements placed on the DRAM. Stacked, in-package High-Bandwidth Memory (HBM) addresses many of thesechallenges. As GPUs scale to bandwidths beyond 1 TB/sec,however, new innovations are required. This talk provides ahigh-level overview of these emerging DRAM architecturechallenges and some approaches to address them.

Biography:

Mike O'Connor manages research efforts at NVIDIA focused on external memory systems, such as DRAM. He has been involved in a range of research on many areas of GPU and memory systems architecture at NVIDIA. Previously at AMD, Mike O'Connor was deeply involved in the development of the HBM standard. Prior to AMD, he was in the product architecture group at NVIDIA where he was the lead memory system architect for several generations of NVIDIA GPUs, including the first NVIDIA GPUs with GDDR5 support. Mike O'Connor has also architected network processors at start-up Silicon Access Networks, an ARM processor core at Texas Instruments, and the picoJava cores at Sun. He has 68 granted patents. He has a BSEE from Rice University and a MSEE from the University of Texas at Austin and is currently working towards finishing his long-delayed PhD at UT-Austin. Mike O'Connor is a Senior Member of the IEEE and a member of the ACM.