Verification of Digital Systems

Course: EIT-EIS-560-V-4
Additional class project (optional): EIT-EIS-562-M-7
Tuesday
Thursday
13:45 - 15:15
14:30 - 16:00
Room: 11-207
Room: 24-102

2 hours of lecture / 2 hours of assignments (5 ECTS credits) plus 3 ECTS class project (optional)
 

Start: Tuesday, October 24, 2023

Examination: Verification of Digital Systems - SS2024
Exam Dates:
 
Thu
Mon
2024-07-23
2024-09-30

Content

Ensuring functional corectness of a complex System-on-Chip consumes 60-80% of the total design costs. This lecture presents basic principles of formal verification techniques and their application within state-of-the-art design flows.  These techniques also set the frame for new, evolving approaches to safety and security analysis in embedded systems (research projects possible).

  • Graph Representations of Boolean Functions
  • Formal Property Checking an Overview
  • Model checking with Temporal Logic
  • Symbolic Traversal of Finite State Machines
  • SAT-based Property Checking
  • Equivalence Checking
  • Laboratory: Introduction into SystemVerilog Assertions (SVA), verification tasks using commercial tool

MORE INFORMATION AND DOWNLOADS ON OPENOLAT.
 

Link to OpenOLAT