Architecture of Digital Systems 1 - Class project
Content
The goal of this class project is to get a first experience in designing hardware from the scratch based on mostly informal specifications. The participants will also (have to) learn to work independently in teams of small size.
The tasks of the class project focus on the content of the AdS1 lecture. Possible topics are arithmetic operations, number representation and basics of processor design. Topics which are discussed later in the lecture, like pipelining and memory hierarchy are not part of the class project.
Organisation
You will work in teams of two to three students. Teams with a different number of students will only be accepted in exceptional cases. In cases where a student cannot find a teammate, he or she can register alone and ask the supervisor for help in order to find a team partner. However, we highly encourage to build teams beforehand and then register as a team.
There will be no supervised lab sessions. However, in cases of problems or questions the students are free to ask the supervisor for help. In fact we highly recommend to inform the supervisor about problems as soon as possible to increase the chances to find a solution in time.
To complete the class project the teams have to complete about 2 tasks. The exact number of tasks will be announced in the lecture when the registration starts.
At the end of each task there will be a meeting where the team present their solution, explain their (design) decisions and discuss different aspects of the task. In case of more complex tasks meetings during the task are also possible. A task is completed when the performance in the last presentation was acceptable.
As soon as a team completes one task, they get the description of the following task.
Supervisor
Prerequisites
It is recommended to have knowledge about hardware design in VHDL (content of the lab course Labor Digitaltechnik1) or Verilog. However, the tasks itself are not designed to be challenging in terms of VHDL or Verilog knowledge, so that students who do not have any knowledge yet, can still successfully complete this class project. Of course, that way the class project will take more time.
Registration
The start of the registration will be announced in the AdS1 lecture. Any registration attempt beforehand will be ignored.
In order to participate send an email to the supervisor containing the following information for each group member:
- First and last name
- Email address
- Student identity number
Places and Times
There is no supervised/assisted computer lab. The class project has to be done by the groups independently during free hours. They can work at home or use the computers in our lab in building 12 room 524 as long as some are vacant. There, every required program is already installed.
Solving some tasks may require the use of non-free or commercial software. In this cases the groups have to use the lab computers, unless they own the particular software, because remote access is not available.
Materials
Tutorials for e.g. ModelSim and testbench creation as well as documents about VHDL and IEEE 754 are available on the computers in the lab and can be copied freely.
Literature
You can find several literature about hardware design in the library of the university. Examples are:
- VHDL for engineers / Kenneth L. Shot - EIT 860/114
- VHDL for logic synthesis / Andrew Rushton - EIT 860/113 & Online
- Verilog HDL / Samir Palnitkar - INF 458/025
An excellent tutorial and reference book for VHDL can be found here. Unfortunately only the german version is excellent. The english version is barely existend.
Additional remarks
After successful completion:
- Bachelor/Master Students: +3 ECTS for AdS1 exam
- Diploma Students: 2 SWS ungraded certificate
If you have any questions, please send an email to Christian Bartsch: bartsch(at)eit.uni-kl.de