Algorithms and hardware architectures for very high throughput binary and non-binary LDPC decoders.

• A new Architecture for High Speed, Low Latency NB-LDPC Check Node Processing for GF(256)
• Error Resilience and Energy Efficiency: An LDPC Decoder Design Study
• Saturated Min-Sum Decoding: An “Afterburner” for LDPC Decoder Hardware
• A New LDPC Decoder Hardware Implementation with Improved Error Rates
• A new Architecture for High Throughput, Low Latency NB-LDPC Check Node Processing
• Syndrome Based Check Node Processing of High Order NB-LDPC Decoders
• Challenges and Limitations for Very High Throughput Decoder Architectures for Soft-Decoding
• Progress in Binary and Non-Binary Low Density Parity Check Codes
• Loopy - An Open-Source TCP/IP Rapid Prototyping and Validation Framework
• A New Dimension of Parallelism in Ultra High Throughput LDPC Decoding
• AXI4-Stream Upsizing/Downsizing Data Width Converters for Hardware-In-the-Loop Simulations
• ASIC implementation of a modified QR decomposition for tree search based MIMO detection
• FPGA-based Rapid Prototyping Platform for MIMO-BICM Design Space Exploration
• Design Space of Flexible Multigigabit LDPC Decoders