Design and Evaluation of a Dynamic SC-Flip Polar Decoder on FPGA Using High-Level Synthesis

Type of work:

Master Thesis

Assignment:
 

In this thesis, the student will design, implement, and evaluate a hardware decoder for polar codes — the channel coding scheme already standardized in 5G and a candidate for future 6G radio interfaces. The thesis covers the following:
 

•  Implementation of a Dynamic Successive Cancellation Flip (DSCF) decoder in C/C++ and its translation to hardware using High-Level Synthesis (HLS) for a modern FPGA
• Bit-accurate simulation and verification of the hardware implementation, including error-rate (FER) simulations against the software reference decoder
• Evaluation and optimization of the implementation in terms of resource utilization, throughput, and latency
• Comparison of the achieved results with related decoder architectures from literature

Skills:

• Solid C/C++ programming skills
• Basic knowledge of digital design and FPGA design flows is helpful
• Interest in channel coding and hardware acceleration
• Prior HLS experience is not required

Supervisor:

C. Kestel

Student:

L. Mullxhi

Year:

2026