2024
Mohamed Taha Chouikh
Design and Implementation of a Smart Home Monitoring and Visualization System with Custom Sensor Nodes (Bachelorarbeit)
Betreuer: C. De Schryver
Amal Mathew
Simulation of ADAS Use Cases for Test and Tool Validation (Masterarbeit)
Betreuer: Dr. C. Weis
Akshay Laxman Powar
Research and Development of Localization System for a Vehicle involving Fusion of Data from Location Sensors (Masterarbeit)
Betreuer: Dr. C. Weis
Javier Ferrer Ortega
Evaluation of Stochastic Computing for Efficient Deep Neural Network Inference (Masterarbeit)
Betreuer: M. H. Sadi, C. Weis
Poorna Jyothirlatha Polavarapu
Exploring Safety and Reliability: Open Source Hypervisor on FPGA (Masterarbeit)
Betreuer: C. De Schryver
Kamal Baghirli
Design and Implementation of a State-of-the-Art Decision Feedback Equalizer (DFE) for a LPDDR5 interface (Masterarbeit)
Betreuer: M. E. Quchani, J. Lappas, C. Weis
Lukas Birkenmeier
Investigation of alternative Decision Feedback Equalizer (DFE) methods for future memory interfaces (Masterarbeit)
Betreuer: J. Lappas, C. Weis
Wael Khlifi
Design and Implementation of an Autonomous Home Monitoring and Access System with Face Recognition (Masterarbeit)
Betreuer: C. De Schryver
Abdulhadi Alsbirij
Design and Implementation of a Pedestrian Recognition System on a Hybrid Xilinx Zynq SoC Demonstrator (Bachelorarbeit)
Betreuer: C. De Schryver
Nabih Talaat Ibrahim Saleh
Design space exploration for efficient hardware implementation of mobile vision transformer on FPGA (Masterarbeit)
Betreuer: V. Rybalkin, M. Ghaffar, M. Moursi
Derek Christ
System Level Integration and Exploration of PIM DRAM (Masterarbeit)
Betreuer: L. Steiner
Michael Petrosyan
Design Space Exploration for Efficient Implementation of Atrial Fibrillation Detection on Low-power Embedded Platforms (Bachelorarbeit)
Betreuer: V. Rybalkin
Furkan Aktas
Implementation of a Digital to Analog Converter for LPDDR4X PHY (Bachelorarbeit)
Betreuer: H. Abdo, J. Lappas, C.Weis
Elias Biehl
MPC Signatures for Embedded Devices: A HW/SW Co-Design (Bachelorarbeit)
Betreuer: M. Schöffel, C. De Schryver
Daniel Koch
Design and Implementation of a Hardware Assisted Cloud Character Exchange Platform for Legacy Gameboy Pokémon Games (Masterarbeit)
Betreuer: C. De Schryver
Sascha Maurice Dauber
Design and Implementation of a LPDDR5 DRAM Controller for ASIC Integration (Diplomarbeit)
Betreuer: C. Weis
Sayed Mohammad Tariful Azam
ASIC-based hardware acceleration of Algebraic Machine Learning (Masterarbeit)
Betreuer: M. Hassani Sadi, C. Weis
Hiandra Tomasi
Custom Processor Instructions for SHA3 on RISC-V Architecture: A Design Space Exploration for FPGA and ASIC Implementation (Masterarbeit)
Betreuer: M.Schöffel
2023
José Cabrera
Implementation of a Doppler Channel Model for Low Earth Orbit Satellites (Masterarbeit)
Betreuer: J. Ney
Ghada Chams Zahrouni
Design and Implementation of a Face Recognition System on a Hybrid Xilinx Zynq SoC Demonstrator (Masterarbeit)
Betreuer: C. De Schryver
Amine Riahi
Investigating Emerging Trends in Logic Circuit simulation with emphasis on interconnect modeling (Masterarbeit)
Betreuer: J. Lappas
Taha Chiheb
Power characterization of external SRAMs with serial interface (Bachlorarbeit)
Betreuer: J. Feldmann
Sascha Dauber
Detailed Behavioral Modelling of an Initialization Unit for a DRAM PHY (Studienarbeit)
Betreuer: C. Weis
Lukas Boos
Development of a System for Ambient Light Control in Modern Vehicles (Masterarbeit)
Betreuer: C. De Schryver
Daniel Vedaa
System-Level Modelling of the ONFI Standard (Masterarbeit)
Betreuer: Matthias Jung, Lukas Steiner
Gizem Amati
Development and Implementation of an Autonomous Temperature Control System for Smart Building Environments (Masterarbeit)
Betreuer: C. De Schryver
Ahmad Abdulla
Embedded Air write: Implementation of Movement Reconstruction (trajectory reconstruction) Algorithm on CPU, GPU and FPGA for real time performance (Masterarbeit)
Betreuer: M.M.Ghaffar
2022
Derek Christ
Development of a System-Level Simulation Frontend for DRAMSys (Bachlorarbeit)
Betreuer: Matthias Jung, Lukas Steiner
Mohamed Moursi
Exploration of Memory Partitioning for Streaming Architectures for Encoder-Decoder Based DNNs (Masterarbeit)
Betreuer: Mohsin Gaffer, Jonas Ney, Vladimir Rybalkin
Ali Shamya
HW/SW Codesign for RISC-V based LPDDR4X-PHY Management Controller (Masterarbeit)
Betreuer: Johannes Feldmann, Jan Lappas
Jakob Sherif
Entwicklung, Implementierung und Evaluation eines Systems zur Prädiktion mithilfe von nicht-invasiver Sensorik (Bachelorarbeit)
Betreuer: Christian De Schryver
Yazan Kazhalawi
Investigation on Layered Decoding Schedules for LDPC Codes (Bachelorarbeit)
Betreuer: Matthias Herrmann, Oliver Griebel
Maria Feting
Acceleration of a High Secure Hashing Algorithm using Near Memory Computing on a Custom RISC-V Platform (Masterarbeit)
Betreuer: Johannes Feldmann, Max Schöffel
Bryan Olmos
Formal Verification of DRAM Controllers Using Timed Petri Nets (Masterarbeit)
Betreuer: Lukas Steiner, Chirag Sudarshan
Mohamed Amine Riahi
A Pass-Transistor-Logic Compatible STA Engine for Path-based Delay Optimization (Bachelorarbeit)
Betreuer: André Chinazzo, Jan Lappas
2021
Iris Walter
Performance-Accuracy Trade-off Analysis, Efficient Design and Implementation of a Deep Neural Network for Face Recognition on FPGAs (Masterarbeit)
Betreuer: Vladimir Rybalkin
Elias Batbouta
Vergleich des Standes der Technik von auf Speichertechnologien basierenden Physical-Unclonable-Functions (Projektarbeit)
Betreuer: Christian Weis
Lucas Weber
Evaluation of Quantum-Safe Digital Signature Algorithms in the Context of TLS-based Low-Power IoT (Masterarbeit)
Betreuer: Maximilian Schöffel, Frederik Lauer
Melanie Neudecker
Entwicklung eines Klassifikationsmodells zur Bestimmung von Qualitätsparametern von Maissilage anhand von Deep Learning auf Grundlage von Hyperspektraldaten (Masterarbeit)
Betreuer: Christian Weis
Luiza Souza Correa
Power Estimation of Modern DRAM Memories (Masterarbeit)
Betreuer: Christian Weis
Rosy Elizabeth Sebastian
Systolic Array Based Quantized Neural Network Accelerator with Custom Memory Hierarchy to Minimize Off-Chip Transfers (Masterarbeit)
Betreuer: Muhammad Mohsin Ghaffar
Patrick Eckes
Design and Evaluation of a Low-cost Infrared Camera-based Positioning System (Masterarbeit)
Betreuer: Frederik Lauer
Stephan Stürz
Analysis and Exploration of hardware-aware Compression Techniques for Deep Neural Networks (Bachelorarbeit)
Betreuer: Jonas Ney
Lukas Boos
Konzeption, Aufbau und Validierung einer intelligenten Gartenbewässerungssteuerung (Bachelorarbeit)
Betreuer: Christian De Schryver
Alexander Ehre
Konzeption und Entwicklung eines RFID basierten Scannersystems für die produzierende Industrie (Studienarbeit)
Betreuer: Christian De Schryver
Julia Rützel
Konzeption und Entwicklung eines SmartBuilding-Simulators auf Basis von KNX (Bachelorarbeit)
Betreuer: Christian De Schryver
Mouayad Horani
Flexible High Throughput Polar Decoders (Masterarbeit)
Betreuer: Claus Kestel
2020
Heba Ganem
Efficient FEFET-based Crossbar and Mixed-signal Blocks Design for an In-memory DNN Hardware Accelerator (Masterarbeit)
Betreuer: Taha Soliman, Chirag Sudarshan
Ahmed EL-Yamany
Exploration of Deep Neural Network Topologies and Efficient Hardware Architecture for Historical Document Baseline Detection (Masterarbeit)
Betreuer: Vladimir Rybalkin
Ebin Zacharias
Deep Learning-based Scene Text Recognition in Mobile Outdoor Application (Masterarbeit)
Betreuer: Vladimir Rybalkin, Menbere Tekleyohannes
Jonas Ney
A Hardware Architecture of a Deep Convolutional Encoder-Decoder Network for Page Segmentation of Historical Handwritten Documents (Masterarbeit)
Betreuer: Vladimir Rybalkin, Muhammad Mohsin Ghaffar
Stefan Pajonk
Exploration and Benchmarking of Memory Architecture Using Virtual Prototyping (Masterarbeit)
Betreuer: Éder Ferreira Zulian
Yannick Robin
Generic On-Chip Memory Generator for ASIC Design Exploration (Masterarbeit)
Betreuer: Jan Lappas
Felipe Salerno Prado
A Domain-Specific Language for Describing DRAM Behavior (Masterarbeit)
Betreuer: Christian Weis, Matthias Jung (IESE)
Khalil Esper
Implementation and Evaluation of Industry 4.0 Service-oriented Production Using Revolution Pi (Masterarbeit)
Betreuer: Christian Weis, Matthias Jung (IESE)
Manoj Hanumaiah
Evaluation and Implementation of an Indoor Localization System for Fraunhofer IESE Concept Cars (Masterarbeit)
Betreuer: Matthias Jung, C. Peper (IESE), Christian Weis
Oliver Broschart
Automated Design and Implementation of a DDR4 Receiver (Masterarbeit)
Betreuer: Jan Lappas, Christian Weis
Lukas Steiner
Simulation of Emerging Memory Standards with DRAMSys (Masterarbeit)
Betreuer: Matthias Jung, Christian Weis
Patrik Eckes
Sensor Fusion Approaches for the Detection of Door and Window Events in Buildings (Bachelorarbeit)
Betreuer: Frederik Lauer, Carl Rheinländer
2019
Kirill Bykov
A SystemC/TLM Framework for Characterising and Validating the RTL Implementation of a Memory Controller (Masterarbeit)
Betreuer: Chirag Sudershan, Matthias Jung
Daniel Rühm
Development of an Input Device with Steam VR Tracking (Masterarbeit)
Betreuer: Christian Weis, Ricardo A. Tauro (ITK)
David Schall
Investigation and Evaluation of hardware-based Memory Encryption and Integrity (Masterarbeit)
Betreuer: Christian Weis, Andreas Sandberg (ARM)
Daniel Gretzke
Design and Implementation of a Blockchain-Based Smart Outlet Concept (Bachelorarbeit)
Betreuer: Carl Rheinländer, Frederik Lauer
Josua Mayer
Development of a transparent Gateway for Internet of Things Devices using IPv6 over Bluetooth Low Energy (Bachelorarbeit)
Betreuer: Carl Rheinländer, Frederik Lauer
Jens Ullmert
Design of an FMC compatible eMMC Adapter Board for Hybrid Memory Emulations (Bachelorarbeit)
Betreuer: Carl Rheinländer
Maxmilian Moritz Schöffel
Design and Implementation of a Hybrid Memory Controller (Masterarbeit)
Betreuer: Deepak M. Mathew
Claudien Nyituriki
A High-Level Implementation of a Hybrid Memory Controller for DRAM and NVM (Diplomarbeit)
Betreuer: Deepak M. Mathew
Surabhi Jain
Parallelism Selection For Performance Improvement Under Area Constraints In Systems With FPGA Accelerators (Masterarbeit)
Betreuer: Christian Weis
Ivi Prifti
RTL Design, Verification, ASIC Implementation of an LPDDR4 Memory Controller and Research on Feasible Schedulers (Masterarbeit)
Betreuer: Chirag Sudarshan
Anjie Qiu
Window Skipping for Unrolled Turbo Decoders (Masterarbeit)
Betreuer: Stefan Weithoffer
2018
Rodrigo Cortes Porto
Integration of SystemC-AMS Simulation Platform into TTool (Masterarbeit)
Betreuer: Christian Weis
Mhd. Rashed Al Koutayni
Hardware Implementation of CNN-Based Hand Pose Estimation on FPGA (Masterarbeit)
Betreuer: Vladimir Rybalkin
Vitor Ribero Roriz
Development of a High-level TCP/IP Driver for a Message-passing Real-time Operating System (Masterarbeit)
Betreuer: Christian Weis
Anes Benmerzoug
Hardware Aware Training and Architecture Exploration For a Multi-Dimensional LSTM Neural Network (Masterarbeit)
Betreuer: Vladimir Rybalkin
Manikantan Ravichandran
RISC-V based Reconfigurable Deep Learning Accelerator Framework Implemented on FPGAs (Masterarbeit)
Betreuer: Christian Weis
Johannes Feldmann
An Application Specific Memory Controller for Video Stream Processing (Masterarbeit)
Betreuer: Christian Weis
Christopher Schmidt
Ein Generatortool für abgerollte vollparallele LDPC Code Decoder (Studienarbeit)
Betreuer: Matthias Herrmann
Yannick Robin
Comparative Study on Different Types of DRAM Sense-Amplifier Implementations for In-Memory-Processing (Bachelorarbeit)
Betreuer: Jan Lappas
Niklas Thiedecke
CORDIC-Hardwareimplementierung mit erweitertem Funktionsumfang und erweitertem Konvergenzbereich (Bachelorarbeit)
Betreuer: Christian Weis
Lukas Krupp
Zeitliche Synchronisation von Basisstationen in drahtlosen Netzwerken für einen echtzeitfähigen Handover-Mechanismus (Bachelorarbeit)
Betreuer: Carl Rheinländer
Doris Gulai
Modeling of LPDDR4-DRAM in DRAMSys (Bachelorarbeit)
Betreuer: Christian Weis
Lukas Steiner
Hardware Implementation & Evaluation of Morphological Reconstruction Filter (Bachelorarbeit)
Betreuer: Menbere Tekleyohannes
Jonas Ney
Exploration of a New All Programmable Heterogeneous MPSoC Computing Platform Xilinx Zynq Ultra Scale+ with Application to Machine Learning (Bachelorarbeit)
Betreuer: Vladimir Rybalkin, Menbere Tekleyohannes
André Lucas Chinazzo
ReRAMSpec: High-Level Modelling of High Density Resistive RAM Cross-Point Arrays (Masterarbeit)
Betreuer: Deepak Mathew, Christian Weis
Frederik Lauer
High Secure Ultra Low Power IoT Infrastructure Exploration (Masterarbeit)
Betreuer: Carl Rheinländer, Claus Kestel
Chetan Dobariya
Design and Implementation of an eDRAM Array using a 2T Gain Cell in UMC’s 65 nm Technology (Masterarbeit)
Betreuer: Christian Weis
Amir Massah Bavani
An Efficient Reconfigurable Hardware Accelerator for Deep Convolutional Neural Network using 3D Systolic Arrays (Masterarbeit)
Betreuer: Vladimir Rybalkin, Muhammad Mohsin Ghaffar
Maycon Douglas Da Silva Carvalho
A heterogeneous embedded computing system for parallel processing of frames extracted from real-time video streams (Masterarbeit)
Betreuer: Carl Rheinländer, Christian Weis
Martin Zeyen
Untersuchung des Noisy Gradient Descent Bit-Flipping Algorithmus zum Decodieren von LDPC Codes (Diplomarbeit)
Betreuer: Kira Kraft, Stefan Weithoffer
Nkrumah Offonry
An Empirical Exploration of Different ECCs for Next-Generation DRAMs and Memories (Masterarbeit)
Betreuer: Christian Weis
Anjie Qiu
Implementation and Evaluation of the Belief-Propagation Algorithm for LTE-Turbo-Codes (Bachelorarbeit)
Betreuer: Stefan Weithoffer