Implementation of a Digital to Analog Converter for LPDDR4X PHY

Type of work:

Bachelor Thesis

Assignment:

In this work, a digital to analog converter is required to produce a trimmable reference voltage (VREF) for an LPDDR4X PHY. It has to be implemented in 12nm FinFet technology. As a first step, state of the art DACs has to be compared and analyzed. Afterwards, the appropriate architecture has to be chosen for the required resolution, and voltage range. Finally, the schematics and layouts of the DAC have to be built, integrated and validated against the required specifications. The final design has to be evaluated in terms of area, power consumption, noise, monotonicity, accuracy, slew rate, and total unadjusted error.

Skills:

• Analog Mixed Signal Design
• Circuit Sizing and Simulation
• FinFet Layout
• Cadence Tools

Background:

Internally, LPDDR4 memories generate their own VREFCA and VREFDQ for the address/command bus and data bus, respectively. Similarly, during reads, the DDR PHY delivers its own reference voltage to the data group nets. That’s why a DAC is required for VREF training and generation in order to account for process, and temperature dependent effects.

Supervisor:

H. Abdo, J. Lappas, C.Weis

Student:

Furkan Aktas

Year:

2023