Investigation of alternative Decision Feedback Equalizer (DFE) methods for future memory interfaces

Type of work:

Master Thesis

Assignment:

• Implementation and integration of DFE in EMS Receiver
• Creation of Simulation Environment for evaluation and validation of DFE circuit
• Analysis of the Results

Skills:

• Mixed Signal Design
• Lectures:  EMSSI+II, Embedded Processor Lab

Background:

The growth of datacenter, storage, automotive and other emerging market applications is driving the development of next-generation memory technologies – DDR5, LPDDR5/6. Like their predecessors, the latest memory technologies also use DFE, to improve the signal integrity (data eye improvement) in their receiver stages. The DFE has to be designed in the analog domain because the cost of ADCs for massive parallel memory interfaces are in terms of power/area too high.

Supervisor:

J. Lappas, C. Weis

Student:

Lukas Birkenmeier

Year:

2024