Implementation and Evaluation of Dynamic Voltage and Frequency Scaling (DVFS) in 12nm FinFET

Type of work:

Master Thesis

Assignment:

During this thesis, the student will investigate and implement Dynamic Frequency Scaling (DFS) techniques on an FPGA platform and subsequently extend the concept towards Dynamic Voltage and Frequency Scaling (DVFS) in a 12 nm FinFET technology node. The work will focus on the development of suitable hardware and control mechanisms that enable runtime adaptation of operating frequency and supply voltage according to system requirements.

A key objective of the thesis is to analyze the practical implications of these techniques with respect to implementation complexity and hardware cost.
In particular, the student will evaluate the latency introduced by frequency and voltage transitions as well as the associated area overhead required for supporting circuitry and control logic. 
Furthermore, the impact of DFS and DVFS on system throughput will be investigated to determine whether performance degradation occurs under realistic workloads.

The thesis will also include a comprehensive power analysis to quantify the achievable energy savings and power reduction resulting from adaptive operating conditions.

Experimental results obtained from technology-specific implementations will be used to assess the trade-offs between performance, area, transition latency, and power efficiency, providing insights into the applicability of DFS and DVFS techniques for future low-power digital systems.

Skills:

• SystemVerilog
• FPGA/ASIC
• Digital Circuit Design

Supervisor:

Johannes Feldmann

Student:

Alejandro Montellano

Year:

2026