Implementation and Evaluation of SRAM based Caches in 12nm FinFET

Type of work:

Master Thesis

Assignment:

During this thesis, the student will design and implement an SRAM-based cache architecture targeting both FPGA platforms and a 12 nm FinFET technology.

The work will focus on the development and optimization of the cache subsystem as well as its integration into a representative processing system.

A comprehensive evaluation will be conducted to investigate key design metrics, including silicon area, access latency, and achievable throughput.

Skills:

• SystemVerilog
• FPGA/ASIC
• Digital Circuit Design

Supervisor:

Johannes Feldmann

Student:

Ajay Yuvraj Jadhav

Year:

2026