Development of an automated workflow for RTL linting and code coverage analysis

Type of work:

Bachelor Thesis

Assignment:
 

In this thesis, the student will design and implement an automated flow for code checking (linting) and code coverage using existing simulation tools from Mentor/Siemens, Cadence or Synopsys. Thus, this Bachelor thesis covers the following:

• Setting up an automated workflow for linters and code coverage (RTL code checks).

  • For example, Questasim from Siemens/Mentor a simulator for ASIC designs, which can be used as a linting tool and for code coverage

• Testing the workflow using group internal examples as well as provided IPs (RISC-V / DRAM controller).

  • The goal is here to improve the code base of the different IPs with this new flow – in addition we may also use software from Synopsys or Cadence

• Evaluation of the results for the specified IP blocks.

  • In addition to our existing blocks, the student should generate here own code examples for further testing as well. 

Skills:

• RTL languages (SystemVerilog, Verilog, VHDL)

• Digital designg

   

   

Supervisor:

C. Weis, J. Feldmann

Student:

Xiangyu Wang

Year:

2026