MPC Signatures for Embedded Devices: A HW/SW Co-Design

Type of work:

Bachelor Thesis

Assignment:

The goal of this work is to employ a HW/SW Co-Design methodology to develop an efficient implementation of an MPC-in-the-head based signature scheme for embedded devices. First, such an algorithm should be implemented and profiled on the processor side (PS) of a heterogeneous platform like the Xilinx ZYNQ. Then, the computational bottlenecks should be identified. For these bottlenecks, loosely coupled accelerators should be designed and implemented in hardware using High-Level Synthesis (HLS) that communicate with the PS via a standard interface such as AXI.

Skills:

• Hardwaredesign
• Programming
• Theory

Background:

Signatures based on Multi-Party Computations (MPC)-in-the-head design paradigms are promising cryptographic algorithms for ensuring authenticity and integrity once large-scale quantum computers become available. Therefore, in the related US NIST Post-Quantum Cryptography (PQC) Process, several MPC-in-the-head-based signature schemes have been proposed. However, compared to conventional and lattice based PQC algorithms, they are more computationally complex and have larger memory requirements. Dedicated hardware accelerators are therefore required, especially for embedded devices, to meet application specific requirements such as latency, memory and power.

Supervisor:

M. Schöffel, C. De Schryver

Student:

Elias Biehl

Year:

2023