• DRAM Simulation
• Error Correction (ECC)
• Photonic Interconnects

Online Working Set Change Detection with Constant Complexity
G. Vasan, É. F. Zulian, C. Weis, M. Jung, N. Wehn. ACM/IEEE International Symposium on Memory Systems (MEMSYS 2021), October, 2021, Washington, DC, USA.

An Energy Efficient 3D-Heterogeneous Main Memory Architecture for Mobile Devices
D. M. Mathew, F. S. Prado, É. F. Zulian, C. Weis, M. M. Ghaffar, M. Jung, N. Wehn. ACM/IEEE International Symposium on Memory Systems (MEMSYS 2020), October, 2020, virtual conference.

The gem5 Simulator: Version 20.0+ A new era for the open-source computer architecture simulator
J. Lowe-Power, A. M. Ahmad, A. Akram, M. Alian, R. Amslinger, M. Andreozzi, A. Armejach, N. Asmussen, S. Bharadwaj, G. Black, G. Bloom, B. R. Bruce, D. R. Carvalho, J. Castrillon, L. Chen, N. Derumigny, S. Diestelhorst, W. Elsasser, M. Fariborz, A. Farmahini-Farahani, P. Fotouhi, R. Gambord, J. Gandhi, D. Gope, T. Grass, B. Hanindhito, A. Hansson, S. Haria, A. Harris, T. Hayes, A. Herrera, M. Horsnell, S. A. R. Jafri, R. Jagtap, H. Jang, R. Jeyapaul, T. M. Jones, M. Jung, S. Kannoth, H. Khaleghzadeh, Y. Kodama, T. Krishna, T. Marinelli, C. Menard, A. Mondelli, T. Mück, O. Naji, K. Nathella, H. Nguyen, N. Nikoleris, L. E. Olson, M. Orr, B. Pham, P. Prieto, T. Reddy, A. Roelke, M. Samani, A. Sandberg, J. Setoain, B. Shingarov, M. D. Sinclair, T. Ta, R. Thakur, G. Travaglini, M. Upton, N. Vaish, I. Vougioukas, Z. Wang, N. Wehn, C. Weis, D. A. Wood, H. Yoon, É. F. Zulian. arXiv Preprint, July, 2020.
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Access-Aware Per-Bank DRAM Refresh for Reduced DRAM Refresh Overhead
É. F. Zulian, C. Weis, N. Wehn. IEEE International Symposium on Circuits & Systems (ISCAS), Poster Session Digital Circuit for Machine Learning & Emerging Memory Circuits, May, 2020, Seville, Spain.

System Simulation with PULP Virtual Platform and SystemC
É. F. Zulian, G. Haugou, C. Weis, M. Jung, N. Wehn. International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC), Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO), January, 2020, Bologna, Italy.

The Role of Memories in Transprecision Computing
C. Weis, M. Jung, É. F. Zulian, C. Sudarshan, D. M. Mathew, N. Wehn. IEEE International Symposium on Circuits and Systems (ISCAS), May, 2018, Florence, Italy.

Using gem5 for Memory Research
É. F. Zulian, M. Jung, N. Wehn. Invited talk, International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Learning gem5 Tutorial (Gem5), March, 2018, Williamsburg, VA, USA.
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Using Run-Time Reverse-Engineering to Optimize DRAM Refresh
D. M. Mathew, É. F. Zulian, M. Jung, K. Kraft, C. Weis, B. Jacob, N. Wehn. International Symposium on Memory Systems (MEMSYS 2017), October, 2017, Washington, DC, USA.

A Bank-Wise DRAM Power Model for System Simulations
D. M. Mathew, É. F. Zulian, S. Kannoth, M. Jung, C. Weis, N. Wehn. International Conference on High-Performance and Embedded Architectures and Compilers 2017 (HiPEAC), Workshop on: Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO), January, 2017, Stockholm, Sweden.

A New Bank Sensitive DRAMPower Model for Efficient Design Space Exploration
M. Jung, D. M. Mathew, É. F. Zulian, C. Weis, N. Wehn. International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS 2016), September, 2016, Bremen, Germany.
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Omitting Refresh - A Case Study for Commodity and Wide I/O DRAMs
M. Jung, É. F. Zulian, D. M. Mathew, M. Herrmann, C. Brugger, C. Weis, N. Wehn. 1st International Symposium on Memory Systems (MEMSYS 2015), October, 2015, Washington, DC, USA.