ZuSE-KI-AVF: Application-Specific AI Processor for Intelligent Sensor Signal Processing in Autonomous Driving
G. B. Thieu, S. Gesper, G. Payá-Vayá, C. Riggers, O. Renke, T. Fiedler, J. Marten, T. Stuckenberg, H. Blume, C. Weis, L. Steiner, C. Sudarshan, N. Wehn, L. M. Reimann, R. Leupers, M. Beyer, D. Köhler, A. Jauch, J. M. Borrmann, S. Jaberansari, T. Berthold, M. Blawat, M. Kock, G. Schewior, J. Benndorf, F. Kautz, H.-M. Bluethgen, C. Sauer. IEEE Conference Design, Automation and Test in Europe (DATE), March, 2023, Antwerp, Belgium.

A Framework for Formal Verification of DRAM Controllers
L. Steiner, C. Sudarshan, M. Jung, D. Stoffel, N. Wehn. ACM/IEEE International Symposium on Memory Systems (MEMSYS 2022), October - December, 2022, virtual conference.

FeFET versus DRAM based PIM Architectures: A Comparative Study
C. Sudarshan, T. Soliman, T. Kampfe, C. Weis, N. Wehn. IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), October, 2022, Patras, Greece.

A Critical Assessment of DRAM-PIM Architectures - Trends, Challenges and Solutions
C. Sudarshan, M. H. Sadi, L. Steiner, C. Weis, N. Wehn. International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XXII), July, 2022, Samos Island, Greece.

A Weighted Current Summation based Mixed Signal DRAM-PIM Architecture for Deep Neural Network Inference
C. Sudarshan, T. Soliman, J. Lappas, C. Weis, M. H. Sadi, M. Jung, A. Guntoro, N. Wehn. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Special Issue "Revolution of AI and Machine Learning with Processing-in-Memory (PIM): from Systems, Architectures, to Circuits", June, 2022.

Optimization of DRAM based PIM Architecture for Energy-Efficient Deep Neural Network Training
C. Sudarshan, M. H. Sadi, C. Weis, N. Wehn. IEEE International Symposium on Circuits and Systems (ISCAS), May, 2022, Austin, TX, USA.

A Novel DRAM Architecture for Improved Bandwidth Utilization and Latency Reduction Using Dual-Page Operation
C. Sudarshan, L. Steiner, M. Jung, J. Lappas, C. Weis, N. Wehn. IEEE International Symposium on Circuits and Systems (ISCAS), May, 2021, Daegu, South Korea. Published in: IEEE Transactions on Circuits and Systems II: Express Briefs (Volume: 68, Issue: 5, May 2021).

A Novel DRAM-Based Process-in-Memory Architecture and its Implementation for CNNs
C. Sudarshan, T. Soliman, C. De la Parra, C. Weis, L. Ecco, M. Jung, N. Wehn, A. Guntoro. 26th Asia and South Pacific Design Automation Conference (ASP-DAC), January, 2021, Virtual Conference.

Ultra Low Power Flexible Precision FeFET based Analog In-memory Computing
T. Soliman, F. Müller, T. Kirchner, T. Hoffmann, H. Ganem, E. Karimov, T. Ali, M. Lederer, C. Sudarshan, T. Kämpfe, A. Guntoro, N. Wehn. IEEE International Electron Devices Meeting (IEDM), December, 2020, virtual conference.

Efficient Generation of Application Specific Memory Controllers
M. V. Natale, M. Jung, K. Kraft, F. Lauer, J. Feldmann, C. Sudarshan, C. Weis, S. O. Krumke, N. Wehn. ACM/IEEE International Symposium on Memory Systems (MEMSYS 2020), October, 2020, virtual conference.

Multi-Valued Physical Unclonable Functions based on Dynamic Random Access Memory
S. Müelich, C. Sudarshan, C. Weis, M. Bossert, R. F. H. Fischer, N. Wehn. ACM/IEEE International Symposium on Memory Systems (MEMSYS 2020), October, 2020, virtual conference.

An In-DRAM Architecture for Quantized CNNs using Fast Winograd Convolutions
M. M. Ghaffar, C. Sudarshan, C. Weis, M. Jung, N. Wehn. ACM/IEEE International Symposium on Memory Systems (MEMSYS 2020), October, 2020, virtual conference.

Efficient Hardware Architectures for 1D- and MD-LSTM Networks
V. Rybalkin, C. Sudarshan, C. Weis, J. Lappas, N. Wehn, L. Cheng. Springer "Journal of Signal Processing Systems", 2020.
Link

eBrainII: A 3 kW Realtime Custom 3D DRAM integrated ASIC implementation of a Biologically Plausible Model of a Human Scale Cortex
D. Stathis, C. Sudarshan, Y. Yang, M. Jung, S. Asad, M. H. Jafri, C. Weis, A. Hemani, A. Lansner, N. Wehn. Springer "Journal of Signal Processing Systems", 2020.
Link

Channel Models for Physical Unclonable Functions based on DRAM Retention Measurements
S. Müelich, S. Bitzer, C. Sudarshan, C. Weis, N. Wehn, M. Bossert, R. F. H. Fischer. XVI International Symposium "Problems of Redundancy in Information and Control Systems" (REDUNDANCY), October, 2019, Moscow, Russia.

Fast Validation of DRAM Protocols with Timed Petri Nets
M. Jung, K. Kraft, T. Soliman, C. Sudarshan, C. Weis, N. Wehn. ACM International Symposium on Memory Systems (MEMSYS 2019), October, 2019, Washington, DC, USA.
Best Paper Award

A Lean, Low Power, Low Latency DRAM Memory Controller for Transprecision Computing
C. Sudarshan, J. Lappas, C. Weis, D. M. Mathew, M. Jung, N. Wehn. International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), July, 2019, Samos Island, Greece.

An In-DRAM Neural Network Processing Engine
C. Sudarshan, J. Lappas, M. M. Ghaffar, V. Rybalkin, C. Weis, M. Jung, N. Wehn. IEEE International Symposium on Circuits and Systems (ISCAS), May, 2019, Sapporo, Japan.

Driving Into the Memory Wall: The Role of Memory for Advanced Driver Assistance Systems and Autonomous Driving
M. Jung, S. A. McKee, C. Sudarshan, C. Dropmann, C. Weis, N. Wehn. ACM International Symposium on Memory Systems (MEMSYS 2018), October, 2018, Washington, DC, USA.

Efficient Coding Scheme for DDR4 Memory Subsystems
K. Kraft, D. M. Mathew, C. Sudarshan, M. Jung, C. Weis, N. Wehn, F. Longnos. ACM International Symposium on Memory Systems (MEMSYS 2018), October, 2018, Washington, DC, USA.
Best Paper Award

Artificial Neural Network Specific Memory Systems
C. Sudarshan. Young Researchers Symposium, June, 2018, Kaiserslautern, Germany.

The Role of Memories in Transprecision Computing
C. Weis, M. Jung, É. F. Zulian, C. Sudarshan, D. M. Mathew, N. Wehn. IEEE International Symposium on Circuits and Systems (ISCAS), May, 2018, Florence, Italy.

Improving the Error Behavior of DRAM by Exploiting its Z-Channel Property
K. Kraft, M. Jung, C. Sudarshan, D. M. Mathew, C. Weis, N. Wehn. IEEE Conference Design, Automation and Test in Europe (DATE), March, 2018, Dresden, Germany.

An Analysis on Retention Error Behavior and Power Consumption of Recent DDR4 DRAMs
D. M. Mathew, M. Schultheis, C. Rheinländer, C. Sudarshan, M. Jung, C. Weis, N. Wehn. IEEE Conference Design, Automation and Test in Europe (DATE), March, 2018, Dresden, Germany.