Under way

Design and Implementation of a State-of-the-Art Decision Feedback Equalizer (DFE) for a LPDDR5 interface

Type of work:

Master Thesis

 
Assignment:
  • Implementation of a state-of-the-art DFE
  • Creation of Simulation Environment for evaluation and validation of DFE circuit
  • Analysis and comparison of the Results
 
Skills:
  • Mixed Signal Design
  • Lectures:  EMSSI+II, Embedded Processor Lab
 
Background:

LPDDR5 brings higher bandwidth and throughput to mobile and automotive devices, which enables the implementation of today's 5G, AI and advanced camera technologies. Like their predecessors, this memory technology also uses DFE to improve the signal integrity (data eye improvement) in their receiver stages. The DFE has to be designed in the analog domain because the cost of ADCs for massive parallel memory interfaces are in terms of power/area too high.

 
Supervisor:

J. Lappas, C. Weis

 
Student:

Kamal Baghirli

 
Year:

2024