A Novel Data Strobe Synchronization Scheme for DRAM Interfaces in 12nm FinFET Technology
M. Esmaeilpour, M. Mestice, J. Lappas, H. Abdo, C. Weis, N. Wehn. Accepted for Publication, 22nd International SoC Design Conference (ISOCC), October, 2025, Busan, Korea.

A 4.266 Gbps/pin LPDDR4X PHY with an Integrated RISC-V Subsystem Optimized for Large Bump Pitch in 12nm FinFET Technology
M. Mestice, J. Feldmann, J. Lappas, M. Esmaeilpour, C. Weis, N. Wehn. Accepted for Publication, 2025 IEEE 38th International System-on-Chip Conference (SOCC),  Sep. 29 - Oct. 1, 2025, Dubai, U.A.E.

A 15 Gb/s Single-Ended Active-Inductive Equalizer with an Optimized Gain-Enhancing Technique
M. Esmaeilpour, M. Mestice, J. Lappas, C. Weis, N. Wehn. 23rd IEEE International NEWCAS Conference, June, 2025, Paris, France.

Design of a Low-Power 4.3 Gb/s Transceiver Using Pre-computed Lookup Tables
H. Abdo, J. Lappas, M. Esmaeilpour, C. Weis, N. Wehn. 28th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), May, 2025, Lyon, France.
Best Paper Award

A 10 Gb/s Low-Power Single-Ended Linear Equalizer for DRAM Interfaces
M. Esmaeilpour, J. Lappas, C. Weis, N. Wehn. IEEE Nordic Circuits and Systems Conference (NorCAS 2024), October, 2024, Lund, Sweden.

A Low-Power Linear Phase Interpolation-Based Delay Line in 12nm FinFET Technology
M. Esmaeilpour, J. Lappas, C. Weis, N. Wehn. 32nd IFIP/IEEE Conference on Very Large Scale Integration (VLSI-SoC 2024), October, 2024, Tanger, Morocco.

Enhanced LPDDR4X PHY in 12 nm FinFET
J. Feldmann, J. Lappas, M. Esmaeilpour, H. Abdo, C. Weis, N. Wehn. RISC-V Summit Europe, June, 2024, Munich, Germany.

A 5 Gb/s Low-Power Receiver with a Novel Data Sampling Method for LPDDR Interfaces
M. Esmaeilpour, J. Lappas, H. Abdo, C. Weis, N. Wehn. 22nd IEEE International NEWCAS Conference, June, 2024, Sherbrooke, Canada.