Jan Lappas, M.Sc.


Building 12, Room 207
67663 Kaiserslautern


Phone: (+49) 631 / 205-5147
Fax: (+49) 631 / 205-4437
Email: jan.lappas(at)rptu.de

Research Areas

  • Memory Controller Hardware
  • Mixed-Signal Chip Design
  • PHY Design of Recent DDR3/4 Interfaces
  • DRAM Circuit Level Models


Timing Analysis with Analytical Sensitivity
J.Lappas, S.Nassif, N.Wehn, 21st International SoC Conference (ISOCC 2024), August, 2024, Sapporo, Japan.

Enhanced LPDDR4X PHY in 12 nm FinFET
J. Feldmann, J. Lappas, M. Esmaeilpour, H. Abdo, C. Weis, N. WehnRISC-V Summit Europe, June, 2024, Munich, Germany.

A 5 Gb/s Low-Power Receiver with a Novel Data Sampling Method for LPDDR Interfaces
M. Esmaeilpour, J. Lappas, H. Abdo, C. Weis, N. Wehn. 22nd IEEE International NEWCAS Conference, June, 2024, Sherbrooke, Canada.

Timing Analysis beyond Complementary CMOS Logic Styles
J. Lappas, A. Riahi, C. Weis, N. Wehn, S. Nassif. 29th Asia and South Pacific Design Automation Conference (ASP-DAC), Januar, 2024, Incheon Songdo , South Korea

Investigation of Pass Transistor Logic in a 12nm FinFET CMOS Technology
A. Chinazzo, J. Lappas, C. Weis, Q. Huang, Z. Wu, L. Ni, N. Wehn. IEEE International Conference on Electronics Circuits and Systems (ICECS 2022), October, 2022, Glasgow, UK.

A Weighted Current Summation based Mixed Signal DRAM-PIM Architecture for Deep Neural Network Inference
C. Sudarshan, T. Soliman, J. Lappas, C. Weis, M. H. Sadi, M. Jung, A. Guntoro, N. Wehn.IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Special Issue "Revolution of AI and Machine Learning with Processing-in-Memory (PIM): from Systems, Architectures, to Circuits", June, 2022.

Machine learning based soft error rate estimation of pass transistor logic in high-speed communication
Z. Zhang, J. Lappas, A. Chinazzo, C. Weis, Z. Wu, L. Ni, N. Wehn, M. Tahoori. 27th IEEE European Test Symposium, May, 2022, Barcelona, Spain.

Revisiting Pass-Transistor Logic Styles in a 12nm FinFET Technology Node
J. Lappas, A. Chinazzo, C. Weis, C. Xia, Z. Wu, L. Ni, N. Wehn. Design, Automation and Test in Europe Conference 2022 (DATE 22), March, 2022, Antwerp, Belgium.

A Novel DRAM Architecture for Improved Bandwidth Utilization and Latency Reduction Using Dual-Page Operation
C. Sudarshan, L. Steiner, M. Jung, J. Lappas, C. Weis, N. Wehn. IEEE International Symposium on Circuits and Systems (ISCAS), May, 2021, Daegu, South Korea. Published in: IEEE Transactions on Circuits and Systems II: Express Briefs (Volume: 68, Issue: 5, May 2021).

Efficient Hardware Architectures for 1D- and MD-LSTM Networks
V. Rybalkin, C. Sudarshan, C. Weis, J. Lappas, N. Wehn, L. Cheng. Springer "Journal of Signal Processing Systems", 2020.

A Lean, Low Power, Low Latency DRAM Memory Controller for Transprecision Computing
C. Sudarshan, J. Lappas, C. Weis, D. M. Mathew, M. Jung, N. Wehn. International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), July, 2019, Samos Island, Greece.

An In-DRAM Neural Network Processing Engine
C. Sudarshan, J. Lappas, M. M. Ghaffar, V. Rybalkin, C. Weis, M. Jung, N. Wehn. IEEE International Symposium on Circuits and Systems (ISCAS), May, 2019, Sapporo, Japan.

Other Publications

A. Renner, J. Lappas, A. König, "Cell Optimization for the IISIC CMOS-Chip Serving as a Front-End for Integrated Impedance Spectroscopy", AMA Proc. of SENSOR 2015 17th Int. Conf. on Sensors and Measurement Technology, AMA Service GmbH, pp. 166-171, 2015, ISBN 978-3-9813484-8-4.