Zhe Zhang, M.Sc.


Institut für Technische Informatik (ITEC)
Karlsruhe Institute of Technology (KIT)
Haid-und-Neu-Str. 7 (Gebäude 07.21)
76131 Karlsruhe


  • Reliable Logic Circuits
  • Pass Transistor Logic
  • Communication Systems


Do Radiation and Aging Impact DVFS? TCAD-based Analysis on 22nm FDSOI Latches
Z. Zhang, C. Weis, N. Wehn, M. Tahoori, S. Nassif. IEEE International Symposium on On-Line Testing and Robust System Design, July 2024.

Addressing the Combined Effect of Transistor and Interconnect Aging in SRAM towards Silicon Lifecycle Management
Z. Zhang, M. Mayahinia, C. Weis, N. Wehn, M. Tahoori, S. Nassif, G. Tshagharyan, G. Harutyunyan, Y. Zorian. IEEE VLSI Test Symposium, April, 2024, Tempe, AZ, USA.

Machine learning based soft error rate estimation of pass transistor logic in high-speed communication
Z. Zhang, J. Lappas, A. Chinazzo, C. Weis, Z. Wu, L. Ni, N. Wehn, M. Tahoori. 27th IEEE European Test Symposium, May, 2022, Barcelona, Spain.