A Novel Data Strobe Synchronization Scheme for DRAM Interfaces in 12nm FinFET Technology
M. Esmaeilpour, M. Mestice, J. Lappas, H. Abdo, C. Weis, N. Wehn. Accepted for Publication, 22nd International SoC Design Conference (ISOCC), October, 2025, Busan, Korea.

Design of a Low-Power 4.3 Gb/s Transceiver Using Pre-computed Lookup Tables
H. Abdo, J. Lappas, M. Esmaeilpour, C. Weis, N. Wehn. 28th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS), May, 2025, Lyon, France.
Best Paper Award

Enhanced LPDDR4X PHY in 12 nm FinFET
J. Feldmann, J. Lappas, M. Esmaeilpour, H. Abdo, C. Weis, N. Wehn. RISC-V Summit Europe, June, 2024, Munich, Germany.

A 5 Gb/s Low-Power Receiver with a Novel Data Sampling Method for LPDDR Interfaces
M. Esmaeilpour, J. Lappas, H. Abdo, C. Weis, N. Wehn. 22nd IEEE International NEWCAS Conference, June, 2024, Sherbrooke, Canada.