A 10 Gb/s Low-Power Single-Ended Linear Equalizer for DRAM Interfaces
M. Esmaeilpour, J. Lappas, C. Weis, N. Wehn. Accepted for Publication, IEEE Nordic Circuits and Systems Conference (NorCAS 2024), October, 2024, Lund, Sweden.

A Low-Power Linear Phase Interpolation-Based Delay Line in 12nm FinFET Technology
M. Esmaeilpour, J. Lappas, C. Weis, N. Wehn. 32nd IFIP/IEEE Conference on Very Large Scale Integration (VLSI-SoC 2024), October, 2024, Tanger, Morocco.

Enhanced LPDDR4X PHY in 12 nm FinFET
J. Feldmann, J. Lappas, M. Esmaeilpour, H. Abdo, C. Weis, N. Wehn. RISC-V Summit Europe, June, 2024, Munich, Germany.

A 5 Gb/s Low-Power Receiver with a Novel Data Sampling Method for LPDDR Interfaces
M. Esmaeilpour, J. Lappas, H. Abdo, C. Weis, N. Wehn. 22nd IEEE International NEWCAS Conference, June, 2024, Sherbrooke, Canada.