Dr.-Ing. Marco Mestice
Anschrift
Erwin-Schrödinger-Straße
Gebäude 12, Raum 251
67663 Kaiserslautern
Kontakt
Telefon: (+49) 631 / 205-5918
Email: marco.mestice(at)rptu.de
Forschungsgebiete
- Analog-RF and Mixed-Signal IC Design
- Phase- and Frequency-Locked Loops
- Design and Measurement of ICs in Harsh-Environments
Publikationen
A Novel Data Strobe Synchronization Scheme for DRAM Interfaces in 12nm FinFET Technology
M. Esmaeilpour, M. Mestice, J. Lappas, H. Abdo, C. Weis, N. Wehn. Accepted for Publication, 22nd International SoC Design Conference (ISOCC), October, 2025, Busan, Korea.
A 4.266 Gbps/pin LPDDR4X PHY with an Integrated RISC-V Subsystem Optimized for Large Bump Pitch in 12nm FinFET Technology
M. Mestice, J. Feldmann, J. Lappas, M. Esmaeilpour, C. Weis, N. Wehn. Accepted for Publication, 2025 IEEE 38th International System-on-Chip Conference (SOCC), Sep. 29 - Oct. 1, 2025, Dubai, U.A.E.
A 15 Gb/s Single-Ended Active-Inductive Equalizer with an Optimized Gain-Enhancing Technique
M. Esmaeilpour, M. Mestice, J. Lappas, C. Weis, N. Wehn. 23rd IEEE International NEWCAS Conference, June, 2025, Paris, France.