iDocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing
M. Tekleyohannes, V. Rybalkin, M. M. Ghaffar, J. Varela, N. Wehn, A. Dengel. MDPI Journal of Imaging, Special Issue: Image Processing Using FPGAs, 2021.
Link

When massive GPU parallelism ain't enough: A Novel Hardware Architecture of 2D-LSTM Neural Network
V. Rybalkin, J. Ney, M. Tekleyohannes, M. M. Ghaffar, N. Wehn. ACM Journal Transactions on Reconfigurable Technology and Systems (TRETS), 2021.
Link

iDocChip - A Configurable Hardware Architecture for Historical Document Image Processing: Multiresolution Morphology-based Text and Image Segmentation
M. Tekleyohannes, V. Rybalkin, M. M. Ghaffar, J. Varela, N. Wehn, A. Dengel. International Journal of Parallel Programming, Springer, 2021.
Link

iDocChip - A Configurable Hardware Architecture for Historical Document Image Processing: Text Line Extraction
M. Tekleyohannes, V. Rybalkin, S. S. Bukhari, M. M. Ghaffar, N. Wehn and A. Dengel. International Conference on Reconfigurable Computing and FPGAs (ReConFig 2019), December, 2019, Cancun, Mexico.

iDocChip - A Configurable Hardware Architecture for Historical Document Image Processing: Multiresolution Morphology-based Text and Image Segmentation
M. Tekleyohannes, V. Rybalkin, S. Bukhari, M. M. Ghaffar, J. Varela, N. Wehn, A. Dengel. International Embedded Systems Symposium (IESS 2019), September, 2019, Friedrichshafen, Germany.
Best Paper Award

A Reconfigurable Accelerator for Morphological Operations
M. Tekleyohannes, C. Weis, Norbert Wehn, M. Klein, M. Siegrist. IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)(RAW2018), May, 2018, Vancouver, Canada.

An Advanced Embedded Architecture for Connected Component Analysis in Industrial Applications
M. Tekleyohannes, M. Sadri, M. Klein, M. Siegrist, C. Weis, N. Wehn. IEEE Conference Design, Automation and Test in Europe (DATE), March, 2017, Lausanne, Switzerland.