iDocChip: A Configurable Hardware Accelerator for an End-to-End Historical Document Image Processing
M. Tekleyohannes, V. Rybalkin, M. M. Ghaffar, J. Varela, N. Wehn, A. Dengel. MDPI Journal of Imaging, Special Issue: Image Processing Using FPGAs, 2021.
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iDocChip - A Configurable Hardware Architecture for Historical Document Image Processing: Multiresolution Morphology-based Text and Image Segmentation
M. Tekleyohannes, V. Rybalkin, M. M. Ghaffar, J. Varela, N. Wehn, A. Dengel. International Journal of Parallel Programming, Springer, 2021.
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iDocChip - A Configurable Hardware Architecture for Historical Document Image Processing: Multiresolution Morphology-based Text and Image Segmentation
M. Tekleyohannes, V. Rybalkin, S. Bukhari, M. M. Ghaffar, J. Varela, N. Wehn, A. Dengel. International Embedded Systems Symposium (IESS 2019), September, 2019, Friedrichshafen, Germany.
Best Paper Award

Running Financial Risk Management Applications on FPGA in the Amazon Cloud
J. Varela, N. Wehn. White Paper, January, 2018.
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Real-Time Financial Risk Measurement of Dynamic Complex Portfolios with Python and PyOpenCL
J. Varela, N. Wehn, S. Desmettre, R. Korn. In PyHPC'17: 7th Workshop on Python for High-Performance and Scientific Computing, November, 2017, Denver, CO, USA.
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Exploiting Decoupled OpenCL Work-Items with Data Dependencies on FPGAs: A Case Study
J. Varela, N. Wehn, Q. Liang, S. Tang. 2017 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)(RAW2017), May-June, 2017, Orlando, USA. [Best paper candidate]

Near Real-Time Risk Simulation of Complex Portfolios on Heterogeneous Computing Systems with OpenCL
J. Varela, N. Wehn. 5th International Workshop on OpenCL (IWOCL 2017), May, 2017, Toronto, Canada.

Nested MC-Based Risk Measurement of Complex Portfolios: Acceleration and Energy Efficiency
S. Desmettre, R. Korn, J. Varela, N. Wehn. Risks Vol. 4, no. 4, pages 36, October, 2016.
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Exploiting the Brownian Bridge Technique to improve Longstaff-Schwartz American Option Pricing on FPGA Systems
J. Varela, C. Brugger, C. De Schryver, N. Wehn, S. Tang, S. Omland. Proceedings of the 2015 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2015), December, 2015, Cancun, Mexico.

Optimization Strategies for Portable Code for Monte Carlo-Based Value-at-Risk Systems
J. Varela, C. Kestel, C. De Schryver, N. Wehn, S. Desmettre, R. Korn. Proceedings of the 8th Workshop on High Performance Computational Finance (WHPCF '15), November, 2015, Austin, USA.

Pricing High-Dimensional American Options on Hybrid CPU/FPGA Systems
J. Varela, C. Brugger, S. Tang, N. Wehn, R. Korn. In FPGA Based Accelerators for Financial Applications, pages 143–166, Springer International Publishing, 1st edition, July, 2015.
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A Quantitative Cross-Architecture Study of Morphological Image Processing on CPUs, GPUs, and FPGAs
C. Brugger, L. Dal'Aqua, J. Varela, C. De Schryver, N. Wehn, Martin Klein, Michael Siegrist. In Proceedings of the 2015 IEEE Symposium on Computer Applications & Industrial Electronics (ISCAIE), April, 2015, Langkawi, Malaysia.

Reverse Longstaff-Schwartz American Option Pricing on hybrid CPU/FPGA Systems
C. Brugger, J. Varela, N. Wehn, S. Tang, R. Korn. IEEE Conference Design, Automation and Test in Europe (DATE), March, 2015, Grenoble, France.