• In-Memory Computing
• Approximate Computing
• Deep neural Networks Acceleration
• Hardware Design & Prototyping

Increasing Throughput of In-Memory DNN Accelerators by Flexible Layer-wise DNN Approximation
C. De la Parra, T. Soliman, A. Guntoro, A. Kumar, N. Wehn. Accepted for publication, IEEE Micro, August, 2022.

FeFET versus DRAM based PIM Architectures: A Comparative Study
C. Sudarshan, T. Soliman, T. Kampfe, C. Weis, N. Wehn.IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), October, 2022, Patras, Greece.

Efficient Hardware Approximation for Bit-Decomposition Based Deep Neural Network Accelerators
T. Soliman, A. Eldebiky, C. De La Parra, A. Guntoro, N. Wehn. Accepted for publication, IEEE International System-On-Chip Conference (SOCC 2022), September, 2022, Belfast, UK.

FELIX: A Ferroelectric FET Based Low Power Mixed-Signal In-Memory Architecture for DNN Acceleration
T. Soliman, N. Laleni, T. Kirchner, F. Müller, A. Shrivastava, T. Kämpfe, A. Guntoro, N. Wehn. ACM Transactions on Embedded Computing Systems, April, 2022.

A Weighted Current Summation based Mixed Signal DRAM-PIM Architecture for Deep Neural Network Inference
C. Sudarshan, T. Soliman, J. Lappas, C. Weis, M. H. Sadi, M. Jung, A. Guntoro, N. Wehn. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Special Issue "Revolution of AI and Machine Learning with Processing-in-Memory (PIM): from Systems, Architectures, to Circuits", June, 2022.

In-Memory Computing exceeding 10000 TOPS/W using Ferroelectric Field Effect Transistors for EdgeAI Applications
N. Laleni, T. Soliman, F. Mueller, S. Mojumder, T. Kirchner, M. Lederer, T. Hoffmann, A. Guntoro, N. Wehn, T. Kaempfe. MikroSystemTechnik Congress 2021, November, 2021, Ludwigsburg, Germany.

Adaptable Approximation Based on Bit Decomposition for Deep Neural Network Accelerators
T. Soliman, C. De La Parra, A. Guntoro, N. Wehn. IEEE International Conference on Artificial Intelligence Circuits and Systems, June, 2021, virtual conference.

Exploiting Resiliency for Kernel-wise CNN Approximation enabled by Adaptive Hardware Design
C. De la Parra, A. El-Yamany, T. Soliman, A. Kumary, N. Wehn, A. Guntoro. IEEE International Symposium on Circuits and Systems (ISCAS), May, 2021, Daegu, South Korea.

A Novel DRAM-Based Process-in-Memory Architecture and its Implementation for CNNs
C. Sudarshan, T. Soliman, C. De la Parra, C. Weis, L. Ecco, M. Jung, N. Wehn, A. Guntoro. 26th Asia and South Pacific Design Automation Conference (ASP-DAC), January, 2021, Virtual Conference.

Ultra Low Power Flexible Precision FeFET based Analog In-memory Computing
T. Soliman, F. Müller, T. Kirchner, T. Hoffmann, H. Ganem, E. Karimov, T. Ali, M. Lederer, C. Sudarshan, T. Kämpfe, A. Guntoro, N. Wehn. IEEE International Electron Devices Meeting (IEDM), December, 2020, virtual conference.

A Ferroelectric FET Based In-memory Architecture for Multi-Precision Neural Networks
T. Soliman, R. Olivo, M. Lederer, T. Kämpfe, T. Kirchner, A. Guntoro, N. Wehn. 2020 IEEE 33rd International System-on-Chip Conference (SOCC), September, 2020, virtual conference.

Efficient FeFET Crossbar Accelerator for Binary Neural Networks
T. Soliman, R. Olivio, T. Kirchner, C. De la Parra, M. Lederer, T. Kämpfe, A. Guntoro, N. Wehn. 31st IEEE International Conference on Application-specific Systems, Architectures and Processors, July, 2020, Manchester, UK.

Fast Validation of DRAM Protocols with Timed Petri Nets
M. Jung, K. Kraft, T. Soliman, C. Sudarshan, C. Weis, N. Wehn. ACM International Symposium on Memory Systems (MEMSYS 2019), October, 2019, Washington, DC, USA.
Best Paper Award