Efficient Deep Neural Network Training with a Novel 5.3-bit Block Floating Point Data Format
M. H. Sadi, C. Sudarshan, S. Nassif, N. Wehn. Accepted for Publication, IEEE Transactions on Circuits and Systems for Artificial Intelligence.

Novel Adaptive Quantization Methodology for 8-bit Floating-Point DNN Training
M. H. Sadi, C. Sudarshan, N. When. Springer Journal on Design Automation for Embedded Systems

A Critical Assessment of DRAM-PIM Architectures - Trends, Challenges and Solutions
C. Sudarshan, M. H. Sadi, L. Steiner, C. Weis, N. Wehn. International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XXII), July, 2022, Samos Island, Greece.

A Weighted Current Summation based Mixed Signal DRAM-PIM Architecture for Deep Neural Network Inference
C. Sudarshan, T. Soliman, J. Lappas, C. Weis, M. H. Sadi, M. Jung, A. Guntoro, N. Wehn. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Special Issue "Revolution of AI and Machine Learning with Processing-in-Memory (PIM): from Systems, Architectures, to Circuits", June, 2022.

Optimization of DRAM based PIM Architecture for Energy-Efficient Deep Neural Network Training
C. Sudarshan, M. H. Sadi, C. Weis, N. Wehn. IEEE International Symposium on Circuits and Systems (ISCAS), May, 2022, Austin, TX, USA.

FPGA-based Trainable Autoencoder for Communication Systems
J. Ney, S. Dörner, M. Herrmann, M. H. Sadi, J. Clausius, S. ten Brink, N. Wehn. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, February, 2022, Virtual Conference.