Optimization and Implementation of DRAM-Based Interleavers for Free-Space Optical Communication Beyond 100 Gbit/s
L. Steiner, U. Wasenmüller, N. Wehn. IEEE Access, October, 2025.

Special Session – Hardware-Software Co-Design for Machine Learning Systems Made Open-Source
M. Tahoori, V. Meyers, M. S. Roodsari, H. Xu, J. Becker, T. Harbaum, F. Frombach, J. Höfer, G. Sotiropoulos, J. Henkel, Z. Demirdag, H. Khdr, H. Nassar, U. Schlichtmann, J. Geier, P. van Kempen, G. Sigl, S. Kögler, M. Probst, J. Teich, F. Hannig, M. Sabih, B. Sesli, N. Wehn, L. Steiner, W. Kunz, M. S. Ali. Embedded Systems Week (ESWEEK), September, 2025, Taipei, Taiwan.

DFI Performance Monitor for LPDDR4X in 12 nm FinFET
J. Feldmann, L. Steiner, C. Weis, N. Wehn. 22nd International SoC Design Conference (ISOCC 2025), October, 2025, Busan, South Korea.

 A Mathematical Model for XOR-Based Application Specific DRAM Address Mapping Schemes
A. Rotaru, O. Bachtler, L. Steiner, M. Jung, S. O. Krumke, N. Wehn. 11th International Symposium on Memory Systems (MEMSYS),  October, 2025, Washington, D.C., USA.
Best Paper Award

Performance and Power Analysis of LPDDR6
D. Christ, L. Steiner, T. Zimmermann, M. Mörz, N. Wilbert, M. Jung, N. Wehn. IEEE Cross-disciplinary Conference on Memory-Centric Computing (CCMCC), October, 2025, Dresden, Germany.

Split'n'Cover: ISO 26262 Hardware Safety Analysis with SystemC
L. Steiner, K. Kraft, D. Christ, D. Uecker, C. Malek, M. Jung, N. Wehn. International Journal of Parallel Programming (IJPP), Springer, 2025.
Link

DRAMPower 5: An Open-Source Power Simulator for Current Generation DRAM Standards
L. Steiner, T. Psota, M. Mörz, D. Christ, M. Jung, N. Wehn. HiPEAC Conference 2025, 17th Workshop on Rapid Simulation and Performance Evaluation for Design Optimization: Methods and Tools (RAPIDO'25), January, 2025, Barcelona, Spain.
Best Paper Award

The New Costs of Physical Memory Fragmentation
A. Halbuer, I. Ostapyshyn, L. Steiner, L. Wrenger, M. Jung, C. Dietrich, D. Lohmann. 2nd Workshop on Disruptive Memory Systems (DIMES'24), November, 2024, Austin, Texas, USA.
Best Paper Award

PIMSys: A Virtual Prototype for Processing in Memory
D. Christ, L. Steiner, N. Wehn, M. Jung. 10th International Symposium on Memory Systems (MEMSYS 2024), October, 2024, Washington, DC, USA.

A Novel System Simulation Framework for HBM2 FPGA Platforms
H. G. Muñoz Hernandez, V. Iskandar, L. Steiner, P. Holzinger, M. Jung, D. Goehringer, M. Huebner, N. Wehn, M. Reichenbach. International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XXIV), July, 2024, Samos Island, Greece.

Physical Layer Forward Error Correction for Free-Space Optical Links
O. Griebel, A. Sauter, U. Wasenmüller, L. Steiner, J. Poliak, B. Matuz, N. Wehn, SPIE Photonics West, Free-Space Laser Communications XXXVI, Januar 2024, San Francisco, Californien, USA

A Mapping of Triangular Block Interleavers to DRAM for Optical Satellite Communication
L. Steiner, T. Lehnigk-Emden, M. Fehrenz, N. Wehn. IEEE Conference Design, Automation and Test in Europe (DATE), March, 2024, Valencia, Spain.

A Precise Measurement Platform for LPDDR4 Memories
J. Feldmann, L. Steiner, D. Christ, T. Psota, M. Jung, N. Wehn. ACM International Symposium on Memory Systems (MEMSYS 2023), Oktober, 2023, Alexandria, VA, USA

Design-Space Exploration for Remote-Sensing (Part I): A Methodical System-Level Approach
B. Hammoud, L. Steiner, N. Wehn. IEEE RADIO International Conference (RADIO), May, 2023, Balaclava.

Design-Space Exploration for Remote-Sensing (Part II): Microwave Radar Imaging from UAVs for Oil Spill Monitoring
B. Hammoud, L. Steiner, N. Wehn. IEEE RADIO International Conference (RADIO), May, 2023, Balaclava.

ZuSE-KI-AVF: Application-Specific AI Processor for Intelligent Sensor Signal Processing in Autonomous Driving 
G. B. Thieu, S. Gesper, G. Payá-Vayá, C. Riggers, O. Renke, T. Fiedler, J. Marten, T. Stuckenberg, H. Blume, C. Weis, L. Steiner, C. Sudarshan, N. Wehn, L. M. Reimann, R. Leupers, M. Beyer, D. Köhler, A. Jauch, J. M. Borrmann, S. Jaberansari, T. Berthold, M. Blawat, M. Kock, G. Schewior, J. Benndorf, F. Kautz, H.-M. Bluethgen, C. Sauer. IEEE Conference Design, Automation and Test in Europe (DATE), March, 2023, Antwerp, Belgium.

Automatic DRAM Subsystem Configuration with irace 
L. Steiner, G. Delazeri, I. Prando da Silva, M. Jung, N. Wehn. International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC), Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO), January, 2023, Toulouse, France.

A Framework for Formal Verification of DRAM Controllers
L. Steiner, C. Sudarshan, M. Jung, D. Stoffel, N. Wehn. ACM/IEEE International Symposium on Memory Systems (MEMSYS 2022), October - December, 2022, virtual conference.

Unveiling the Real Performance of LPDDR5 Memories
L. Steiner, M. Jung, M. Huonker, N. Wehn. ACM/IEEE International Symposium on Memory Systems (MEMSYS 2022), October - December, 2022, virtual conference.

A Critical Assessment of DRAM-PIM Architectures - Trends, Challenges and Solutions
C. Sudarshan, M. H. Sadi, L. Steiner, C. Weis, N. Wehn. International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS XXII), July, 2022, Samos Island, Greece.

DRAMSys4.0: An Open-Source Simulation Framework for In-Depth DRAM Analyses
L. Steiner, M. Jung, F. S. Prado, K. Bykov, N. Wehn. International Journal of Parallel Programming (IJPP), Springer, 2022.

An LPDDR4 Safety Model for Automotive Applications
L. Steiner, D. Uecker, M. Jung, K. Kraft, M. Huonker, N. Wehn. ACM/IEEE International Symposium on Memory Systems (MEMSYS 2021), October, 2021, Washington, D.C., USA.

A Novel DRAM Architecture for Improved Bandwidth Utilization and Latency Reduction Using Dual-Page Operation
C. Sudarshan, L. Steiner, M. Jung, J. Lappas, C. Weis, N. Wehn. IEEE International Symposium on Circuits and Systems (ISCAS), May, 2021, Daegu, South Korea. Published in: IEEE Transactions on Circuits and Systems II: Express Briefs (Volume: 68, Issue: 5, May 2021).

Exploration of DDR5 with the Open Source Simulator DRAMSys
L. Steiner, M. Jung, N. Wehn. 24. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, March, 2021, Munich, Germany.

DRAMSys4.0: A Fast and Cycle-Accurate SystemC/TLM-Based DRAM Simulator
L. Steiner, M. Jung, F. S. Prado, K. Bykov, N. Wehn. International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), July, 2020, Samos Island, Greece.

Fast and Accurate DRAM Simulation: Can we Further Accelerate it?
J. Feldmann, M. Jung, K. Kraft, L. Steiner, N. Wehn. IEEE Conference Design, Automation and Test in Europe (DATE), March, 2020, Grenoble, France.
Nominated for Best Paper Award